簡易檢索 / 詳目顯示

回結果列表
研究生： 黃奕閔
Huang, Yi-Min
論文名稱： 多晶矽無接面電晶體之通道厚度效應研究
The Impact of Active Layer Thickness on the Electrical Characteristics of Poly-Si Junctionless TFTs
指導教授： 高國興
Kao, Kuo-Hsing
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 奈米積體電路工程碩士博士學位學程
MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年： 2017
畢業學年度： 105
語文別： 英文
論文頁數： 19
中文關鍵詞： 無接面電晶體 、傳統接面電晶體 、通道厚度 、短通道效應
外文關鍵詞： Junction-less transistors, inversion-mode transistor, channel thickness, short channel effect
相關次數： 點閱：150  下載：17 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 在此論文中，我們製做多晶矽無接面電晶體與傳統接面電晶體，並量測和比較他們的電特性透過電特性量測。我們發現次臨界擺幅隨著通道厚度變薄而降低，甚至低於傳統接面電晶體。另一方面，我們也使用了TCAD模擬軟體去驗證元件的操作機制。根據模擬結果，我們發現在長通道(Lg:100nm)時，無接面電晶體的次臨界擺幅會高於傳統接面電晶體的次臨界擺幅。然而在短通道(Lg:50nm)時，無接面電晶體次臨界擺幅會低於傳統接面電晶體次臨。該結果可以歸因於無接面電晶體擁有較長有效通道長度。另一方面，我們也研究並比較在不同通道厚度，無接面電晶體和傳統接面電晶體的電特性。我們發現當通道厚度太厚(20nm)時，無接面電晶體的次臨界擺幅會高於無傳統接面電晶體。這是因為閘極無法完全排除所有載子導致不必要的漏電流。

    In this study, we fabricated junction-less transistors and inversion-mode transistors, and their electrical characteristic was measured and compared. We found that subthreshold swing decreased as the channel thickness became thinner, even lower than that of the traditional inversion-mode transistor. On the other hand, we also used TCAD simulation to verify the mechanism of device operation. According to simulation results, we found the subthreshold swing of the junction-less transistor is higher than that of the inversion-mode transistor with a long channel length of 100 nm. However with a short channel length of 50 nm, the subthreshold swing of the junction-less transistors is lower than that of an inversion-mode transistor. This result can be attributed to the fact that the junction-less transistors has a longer effective channel length. On the other hand, we also investigated and compared the electrical characteristics of junction-less and inversion-mode transistors with different channel thickness. We found that subthreshold swing of the junction-less transistors is higher than that of the inversion-mode transistor when the channel thickness is too thick (20 nm). This is because the gate is not able to completely depleted all carrier underneath resulting unwanted leakage currents.

    Contents 摘要......I Abstract......II 誌謝......III Contents......IV Figure captions......V Chapter 1 Introduction and Motivation......1 1.1 Transistor Scaling.....1 1.2 Operation Principle of transistors......1 1.3 Short channel effect......3 1.4 Compare of junction-less transistors and inversion-mode transistors.......4 1.5 Motivation........6 Chapter 2 Device Fabrication and Experimental Setup......7 2.1 Experimental Procedure.......7 Chapter3 Results and Discussion ......13 3.1 Experimental results.......13 3.2 Simulation Resultt......14 Chapter4 Conclusion and Future Work......18 4.1 Conclusion......18 4.2 Future Work......18 References......19 Figure captions Fig. 1-1 Moore’s Law......1 Fig. 1-2 Energy band diagram of the MOSFET at inversion......2 Fig. 1-3 Cross sections and operation principle of n-type Junction-less FETs......2 Fig. 1-4 Operation mode in (a)inversion (b)accumulation (c)depletion......3 Fig. 1-5 Drain Induced Barrier Lowering(DIBL)......4 Fig. 1-6 Profile of the first subband in JL and IM devices in off-state and on-state.......5 Fig. 1-7 effective gate length variation from the off-state to the on-state in a junction-less transistors......5 Fig. 1-8 (a) junction-less transistors , (b) inversion-mode transistors.......6 Fig. 2-1 Wet oxide 500nm on Si substrate......8 Fig. 2-2 Etch 500Å SiO2.......8 Fig. 2-3 Deposit 1000Å in-situ N+ Poly-Si......9 Fig. 2-4 Etch 1000Å in-situ N+ Poly-Si......9 Fig. 2-5 Deposit in-situ N+ Poly-Si or undoped Si to be a channel.......10 Fig. 2-6 Deposit 150Å Gate oxide by LPCVD......10 Fig. 2-7 Deposit Ti to be gate metal and define gate pattern......11 Fig. 2-8 Gate etching and open the contact holes......11 Fig. 2-9 Deposit AlSiCu and define pad region......12 Fig. 2-10 Etch AlSiCu......12 Fig. 3-1 Id-Vg characteristics of junction-less transistors(JL) and inversion-mode transistors(IM) with different channel thickness......13 Fig. 3-2 Device cross section......14 Fig. 3-3 Id-Vg characteristics of junction-less transistors(JL) and inversion-mode transistors(IM) with different doping concentrations at gate length 100nm. ......15 Fig.3-4 Id-Vg characteristics of junction-less transistors(JL) and inversion-mode transistors(IM) with different doping concentrations at gate length 50nm ......15 Fig. 3-5 Id-Vg characteristics of junction-less transistors(JL) and inversion-mode transistors(IM) with different doping concentrations at gate length 50nm and channel thickness 10nm......16 Fig. 3-6 Id-Vg characteristics of junction-less transistors(JL) and inversion-mode transistors(IM) with different doping concentrations at gate length 50nm and channel thickness 12nm.......16 Fig. 3-7 Id-Vg characteristics of junction-less transistors(JL) and inversion-mode transistors(IM) with different doping concentrations at gate length 50nm and channel thickness 15nm.......17 Fig. 3-8 Id-Vg characteristics of junction-less transistors(JL) and inversion-mode transistors(IM) with different doping concentrations at gate length 50nm and channel thickness 20nm......17

    [1] K. J. Kuhn et al., "Moore's Law Past 32nm: Future Challenges in Device Scaling," in Computational Electronics, 2009. IWCE09.13th International Workshop, pp. 1-6., 2009
    [2] Jean-Pierre Colinge et al., “Nanowire transistors without junctions” NATURE NANOTECHNOLOGY , vol .5 pp.225-229,March 2010
    [3] D. A. Neamen et al., “ Semiconductor physics and devices, ”3rd ed, McGraw-Hill
    [4] K.K. Young et al.,”Short-channel effect in fully depleted SOI MOSFETs” IEEE Transactions on Electron Devices, vol. 36,pp. 399-402,Feb.1989
    [5] Shilpi Guin et al., “Comparison of Logic Performance of CMOS Circuits Implemented With Junctionless and Inversion-Mode FinFETs” IEEE Trans.Electron Device, VOL. 64, NO. 3 pp. 953-959, MARCH 2017
    [6] S. Gundapaneni et al., “Effect of Band-to-Band Tunneling on Junctionless Transistors”IEEE Trans.Electron Device, vol. 59,no. 4,pp. 1023-1029,Apr.2012
    [7] R.R. Troutman et al.,” VLSI limitations from drain-induced barrier lowering” IEEE Journal of Solid-State Circuits , vol. 14,pp. 383-391,Apr.1979
    [8] Pedram Razavi et al., “Influence of channel material properties on performance of nanowire transistors” JOURNAL OF APPLIED PHYSICS 111,124509, May 2012
    [9] R. Rios et al., “Comparison of Junctionless and Conventional Trigate Transistors With Lg Down to 26 nm” IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 9 pp. 1170-1172, SEP 2011
    [10] C-W Lee et al., “Performance estimation of junctionless multigate transistors” Solid-State Electronics 54, pp. 970-103, 2010
    [11] TCAD Sentaurus workbench version-2013

    下載圖示
    校外：立即公開
    QR CODE