半導體產業在台灣的科技業中扮演著極為中要的角色，被視為台灣經濟的支柱產業之一，而封裝在這產業鏈中的末端，扮演著半導體晶片保護、連接、並整合到最終電子產品的關鍵步驟。根據不同類型的應用與需求，存在多種不同類型的封裝技術，如:雙列直插封裝Dual in line package (DIP)、球柵陣列封裝Ball Grid Array (BGA)、四方平面無引腳封裝Quad Flat No Lead (QFN)、扇出型晶圓級封裝Fan-Out Wafer-Level Package (FOWLP)、面板級扇出型封裝Fan-Out Panel-Level Package (FOPLP)，而在封裝設備中，由於材料之間的熱膨脹係數各異，在密封製程後的冷卻期間，產品容易產生翹曲，過去這幾十年, 半導體隨著摩爾定律正飛快的發展，產品功能日益強大的同時也越來越強調輕、薄、短、小，所以對於尺寸精確度的要求也就更加嚴苛。
本研究主要目的為探討不同的材料、尺寸、密度…等對於產品翹曲的影響，並從中找出影響最甚之因子，進一步找到最佳化的組合設計。本研究使用有限元素法搭配田口方法來探討各項參數對於翹曲所產生的影響，考慮產品結構複雜度會對執行有限元素法造成負擔，本研究針對非變因之參數進行簡化，透過等校性分析，將模擬實驗中不會變動之參數及所對應之部件轉化為單一材料之元件，以藉此減輕運算時分析的負擔，同時也因此可以對更大型的裝置進行模擬運算，使結果更貼近實際狀況，經模擬實驗可得知，影響翹曲最明顯的因子為面板大小以及晶體數量，透過田口方法以及最佳化設計，翹曲值由0.102mm下降至0.0965mm，下降了約5.4%也透過後續加法實驗驗證其結果。

Semiconductor industry plays a crucial role in the global technology sector. Packaging, being the final step in the semiconductor manufacturing, is vital for protecting, connecting, and integrating semiconductor chips into end electronic products. Depending on the type of applications and requirements, various packaging technologies exist. During the packaging process, due to the different coefficients of thermal expansion (CTE) among the materials, products are prone to warpage during the cooling phase after molding/sealing. Over the past several decades, semiconductor technology has been rapidly advancing in line with Moore's Law. As products become more powerful, there is also a growing emphasis on making them lighter, thinner, shorter, and smaller, which places even more stringent demands on dimensional accuracy, especially warpage.
The primary objective of this study is to investigate the impact of various factors such as material types, size, density, and others on product warpage and identify the most influential factors, thereby determining the optimal combination design. The study employs the Finite Element Method (FEM) in conjunction with the Taguchi method to explore the effects of different parameters on warpage. As the complexity of the packaging structure may burden the execution of FEM, the study simplifies the non-influential parameters through equivalent analysis to reduce them into the properties of a single material. This approach allows the simulation of larger devices, making the simulations more effective in real-world applications. Simulation results reveal that the most significant factors affecting warpage are the panel size and the number of dies. Through the Taguchi method and optimal design, the warpage value was reduced from 0.102 mm to 0.0965 mm, a decrease of approximately 5.4% which were validated through subsequent additive rules.

[1] F. Hou et al., "Experimental Verification and Optimization Analysis of Warpage for Panel-Level Fan-Out Package," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 10, pp. 1721-1728, 2017, doi: 10.1109/tcpmt.2017.2726084.
[2] C.-C. Lee et al., "Warpage Estimation of Heterogeneous Panel-Level Fan-Out Package with Fine Line RDL and Extreme Thin Laminated Substrate Considering Molding Characteristics," presented at the 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021.
[3] J. Ho, R. Chen, K. Y. Chen, S. Shin, and M. K. Shih, "Mechanical and Warpage Characterization of Glass Carrier in Fan-out Technology Development," in 2018 19th International Conference on Electronic Packaging Technology (ICEPT), 2018: IEEE, pp. 55-58.
[4] M.-Y. Tsai and Y.-W. Wang, "A Theoretical Solution for Thermal Warpage of Flip-Chip Packages," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 1, pp. 72-78, 2020, doi: 10.1109/tcpmt.2019.2933546.
[5] A. Salahouelhadj, M. Gonzalez, K. Vanstreels, G. Van der Plas, G. Beyer, and E. Beyne, "Analysis of warpage of a flip-chip BGA package under thermal loading: Finite element modelling and experimental validation," Microelectronic Engineering, vol. 271-272, 2023, doi: 10.1016/j.mee.2023.111947.
[6] Z. Kuang, G. Yang, R. Cui, Y. Zhang, and C. Cui, "Warpage simulation and optimization of panel level fan-out package in post molding cure," in 2020 21st International Conference on Electronic Packaging Technology (ICEPT), 2020: IEEE, pp. 1-5.
[7] Z. Wang, W. Yang, C. Zhu, S. Wu, Y. Ni, and D. Yang, "Warpage Analysis and Optimization of Fan-Out Panel-Level Packaging in Hygrothermal Environment," presented at the 2023 24th International Conference on Electronic Packaging Technology (ICEPT), 2023.
[8] C.-W. Wang, C.-P. Chang, and C.-C. Lee, "Demonstration on Warpage Estimation Approach Utilized in Fan-Out Panel-Level Packaging Enabled by Multi-Scale Process-Oriented Simulation," presented at the 2023 IEEE International Reliability Physics Symposium (IRPS), 2023.
[9] C. H. Tsai, S. W. Liu, and K. N. Chiang, "Warpage Analysis of Fan-Out Panel-Level Packaging Using Equivalent CTE," IEEE Transactions on Device and Materials Reliability, vol. 20, no. 1, pp. 51-57, 2020, doi: 10.1109/tdmr.2019.2956049.
[10] F. X. Che, K. Yamamoto, V. S. Rao, and V. N. Sekhar, "Panel Warpage of Fan-Out Panel-Level Packaging Using RDL-First Technology," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 2, pp. 304-313, 2020, doi: 10.1109/tcpmt.2019.2929529.
[11] D. Ecoiffier, P. Vernhes, R. Ooi, T. Braun, M. Dreissigacker, and H. Fu, "Experimental study of panel level packaging warpage," in 2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC), 2020: IEEE, pp. 1-4.
[12] F. X. Che, K. Yamamoto, V. S. Rao, and V. N. Sekhar, "Study on Warpage of Fan-Out Panel Level Packaging (FO-PLP) Using Gen-3 Panel," presented at the 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019.
[13] C.-C. Lee, C.-P. Chang, C.-Y. Chen, H.-C. Lee, and G. C.-F. Chen, "Warpage Estimation and Demonstration of Panel-Level Fan-Out Packaging With Cu Pillars Applied on a Highly Integrated Architecture," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 13, no. 4, pp. 560-569, 2023, doi: 10.1109/tcpmt.2023.3269424.
[14] M. Su et al., "Warpage simulation and experimental verification for 320 mm × 320 mm panel level fan-out packaging based on die-first process," Microelectronics Reliability, vol. 83, pp. 29-38, 2018, doi: 10.1016/j.microrel.2018.02.010.
[15] H. Liu, T. Lin, F. Hou, H. Zhang, and L. Cao, "Process Development and Failure Analysis for Chip-Last Panel Level Fan-out Packaging (PLP)," in 2018 19th International Conference on Electronic Packaging Technology (ICEPT), 2018: IEEE, pp. 129-134.
[16] S. W. Liu, S. K. Panigrahy, and K. N. Chiang, "Prediction of Fan-out Panel Level Warpage using Neural Network Model with Edge Detection Enhancement," presented at the 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020.
[17] Y.-K. Deng, B.-X. Yang, W.-L. Hu, and X.-P. Zhang, "A Comprehensive Simulation Study of Warpage of Fan-out Panel-level Package using Element Birth and Death Technique," presented at the 2021 22nd International Conference on Electronic Packaging Technology (ICEPT), 2021.
[18] R. Cui, Z. Kuang, G. Yang, C. Cui, and Y. Zhang, "Warpage Simulation and Optimization of Panel Level Fan-out Embedded Package," in 2020 21st International Conference on Electronic Packaging Technology (ICEPT), 2020: IEEE, pp. 1-5.
[19] T.-C. Chiu and E.-Y. Yeh, "Warpage simulation for the reconstituted wafer used in fan-out wafer level packaging," Microelectronics Reliability, vol. 80, pp. 14-23, 2018, doi: 10.1016/j.microrel.2017.11.008.
[20] J. H. Lau et al., "Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 10, pp. 1729-1738, 2017, doi: 10.1109/tcpmt.2017.2715185.
[21] Z. Yan, C. Zhong, L. Lou, S. Yu, Z. Hu, and R. Sun, "Warpage Simulation and Analysis for FOWLP with Metal Carrier," presented at the 2022 23rd International Conference on Electronic Packaging Technology (ICEPT), 2022.
[22] W.-C. Lo, B.-J. Lwo, H. Chung, T. Ni, and S. Lu, "Warpage Simulation on a Typical Fan-out Panel Level Package (FOPLP) Process with Glass Carrier," in 2019 14th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2019: IEEE, pp. 80-83.
[23] C.-C. Lee, C.-P. Chang, and P.-C. Huang, "Development and Demonstration on Process-Oriented Warpage Simulation Methodology of Fan-Out Panel-Level Package in Multilevel Integration," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 13, no. 12, pp. 2016-2023, 2023, doi: 10.1109/tcpmt.2023.3331692.
[24] H. L. Chen and K. N. Chiang, "The Effect of Geometric and Material Uncertainty on Debonding Warpage in Fan-Out Panel Level Packaging," presented at the 2023 24th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2023.
[25] M. van Dijk et al., "Simulation challenges of warpage for wafer-and panel level packaging," in 2020 21st International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2020: IEEE, pp. 1-6.
[26] L. Bu, F. Che, V. S. Rao, and X. Zhang, "Mold flow simulation for fan-out panel-level packaging (FOPLP)," in 2018 IEEE 20th Electronics Packaging Technology Conference (EPTC), 2018: IEEE, pp. 691-694.
[27] J.-S. Lan and M.-L. Wu, "Warpage Simulation and Analysis for Panel Level Fan-out Package," in 2020 19th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2020: IEEE, pp. 1160-1164.
[28] C.-C. Lee et al., "Comprehensive investigation on warpage management of FOPLP with multi embedded ring designs," in 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019: IEEE, pp. 1413-1418.
[29] C. C. Meng, S. Stoeckl, H. Pape, F. M. Yee, and T. A. Min, "Effect of substrate warpage on flip chip BGA thermal stress simulation," in 2010 12th Electronics Packaging Technology Conference, 2010: IEEE, pp. 500-504.
[30] R. R. Schaller, "Moore's law: past, present and future," IEEE spectrum, vol. 34, no. 6, pp. 52-59, 1997.
[31] T. Braun et al., "Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration," Micromachines (Basel), vol. 10, no. 5, May 23 2019, doi: 10.3390/mi10050342.
[32] "<Ansys_Meshing_Users_Guide.pdf>," 2021.