由於半導體產業製程技術的進步，現代的積體電路(IC) 中電晶體元件數量迅速增加，使得電路中的漏電流(leakage current) 功率消耗問題變得越來越嚴重，在解決此問題的諸多方法之中，電源閘控式設計(power gating designs) 是相當有效的方法。它將非持續運作的電路區分為低功率電源區域(low-power domain)，並藉由電源開關器(power switch) 關斷處於待機模式下的低功率電源區域供應電壓，以降低漏電流的消耗。然而，在電路中加入電源開關器後，亦會衍生出其他考量議題，包含低功率電源域電壓下降 (IR-drop)，增加設計成本，以及對於已經完成擺置之邏輯電路產生影響， 而這些問題又與電源開關器的使用數量與擺放位置皆息息相關。有別於先前的研究多半以貪婪演算法(greedy algorithm) 的方式處理此問題，本論文使用等效電阻去模擬低功率電源區域中之電源開關器，再根據二分搜尋法迭代以尋找滿足電壓下降限制所需之等效電阻值，並且依此值計算出電源開關器的使用數量；最後，為了能在擺置電源開關器時，同步考量電壓與對已擺放之邏輯電路的影響兩項因素，本論文又提出整數型線性規劃(integer linear programming) 的方法去決定電源開關器的擺放位置。實驗結果證實本論文的執行結果相較於先前的相關研究結果，能夠使用更為精簡電源開關器去滿足電壓下降值的限制，除此之外，對已擺放之邏輯電路的影響也更加輕微。

Due to advance in manufacture technology, leakage current becomes a serious problem in modern IC designs. Power gating is a widely applied technique to resolve this problem, which requires to place power switches into a low-power domain to turn off supply voltage. Insertion of power switches is an important step in power gating designs because number and locations of power switches have great impact on chip area and IR-drop of circuits. Unlike previous works using the greedy algorithm to handle this problem, this thesis proposes a simplified model to approximate the required equivalent resistance of power switches in a low-power domain, and determines proper number and types of power switches based on the value. It also adopts the binary search method to find the precise value. Further, in order to reduce its impact on pre-placed standard cells, a mathematical approach is proposed to determine the locations of these power switches. We compare our method with the work of engineers and the greedy method which was implemented by us based on test cases provided by Himax. Experimental results demonstrate that our approach uses less area of power switches to satisfy the IR-drop constraint. Moreover, our approach has small influence to pre-placed standard cells.

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