隨著雲端計算以及大數據應用發展迅速，一些有著大範圍存取的應用如記憶體內建資料庫(in-memory databases)的應用越來越普及，這些應用需要高容量以及高可靠度的記憶體架構，為了達到上述兩種需求，混合式記憶體架構(Hybrid Memory Architecture)採用了動態隨機存取記憶體(DRAM)及非揮發性記憶體(NVM)，同時有著高容量及非揮發性的特性，但NVM通常伴隨較慢的存取速度還有寫入次數的限制，所以如果我們可以減少NVM的寫入次數，可以同時改善存取延遲以及增進NVM的使用期限。其中一種解決NVM的寫入次數的方法是將占用DRAM空間，但長時間不被存取的頁踢出DRAM，並將空間留給有需要的頁，如此一來即可減少錯失率(miss rate)與NVM的寫入次數。近期有好幾種技術可以辨識出dead block的存在，從而減少快取層(cache level)的miss rate，但這些方法在記憶體層都無法發揮其效能，因為當benchmarks經過快取的過濾後喪失了局部性(locality)的特性，為了可以讓死頁預測更為精確並減少NVM的寫入次數，這篇論文提出了一個使用在記憶體層，新穎的死頁預測方法，感染式死頁預測方法(IDP: Infection Based Dead Page Prediction)，感染式死頁預測利用被踢出DRAM的頁利用有著相同存取次數的條件，將周遭有著相同存取次數的頁標記為死頁(周遭的頁即被感染為死頁)，一會兒後這些死頁被踢出DRAM的同時，IDP會繼續尋找新的死頁，再往它們周遭去尋找一樣存取次數的頁，並標記為死頁。IDP較LRU平均減少了20%的miss rate(某些應用超過30%)以及平均增加了9%的NVM壽命(某些應用超過15%)

With widespread of cloud computing and applications that require large memory footprint such as in-memory databases have gained in popularity. These applications depend on high capacity and reliable memory architecture. To achieve these two goals, hybrid memory that uses both DRAM and non-volatile memory (NVM) provides the benefits like large capacity and non-volatility. However, NVM is usually accompanied with high write latency and endurance problem. It is important to reduce NVM writes and improve the latency and lifetime of hybrid memory. One way to reduce NVM writes is to reduce dead pages that occupy DRAM and have not been accessed for a long time. When dead pages are removed from the memory, more space can be reserved for useful data, reducing DRAM misses and NVM writes. Currently, there are several dead block prediction techniques that can identify dead blocks and reduce miss rates in the cache level. However, they are not effective in the memory level because memory access behaviors exhibit less locality after trace of benchmarks filtered by caches. To improve dead page prediction accuracy and reduce NVM writes, this paper proposes a simple but effective dead page prediction method, infection based dead page prediction (IDP), for the memory level. IDP uses the evicted page to predict dead pages in the nearby based on the access counts (i.e. other pages are infected by evicted pages). When the nearby dead pages are evicted, IDP continues searching and finding new dead pages. Simulation results show that IDP reduces 20% DRAM misses in average (over 30% in some applications) and improves 9%(over 15% in some applications) lifetime compared to LRU in average.

[1] N. Agrawal et al., "Design Tradeoffs for SSD Performance," in USENIX Annu. Tech. Conf. 2008, pp.57–70.
[2] J. Ahn et al, “DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture,” in 2014 HPAC, pp. 25-36
[3] B. Aker, “memslap - Load testing and benchmarking a server,” [Online]. Available: http://docs.libmemcached.org/bin/memslap.html
[4] D. A. Bader et al., Hpc graph analysis. http://www.graphanalysis.org/benchmark/index.html. Accessed: 2018-02-16.
[5] S. Beamer et al., “GAP Benchmark,” [Online]. Available: http://gap.cs.berkeley.edu/benchmark.html
[6] S. Boboila and P. Desnoyers, "Write Endurance in Flash Drives: Measurements and Analysis," in FAST 2010.
[7] K. Chen et al, “A Novel Page Replacement Algorithm for the Hybrid Memory Architecture Involving PCM and DRAM,” in 2014 NPC, pp. 108-119
[8] W. Chen, “Global Clean Page First Replacement and Index Aware Multi-Stream Prefetcher in Hybrid Memory Architecture,” unpublished master's thesis, National Cheng Kung University, Tainan, Taiwan, 2018
[9] B. Fitzpatrick, “memcached – a distributed memory object caching system,” [Online]. Available: https://memcached.org
[10] Graph500. http://www.graph500.org/. Accessed: 2018-02-16.
[11] A. Jaleel et al, “High performance cache replacement using re-reference interval prediction (RRIP),” in 2010 ISCA, pp. 60-71
[12] S. Jiang and X. Zhang, “LIRS: an efficient low inter-reference recency set replacement policy to improve buffer cache performance,” in 2002 SIGMETRICS, pp. 31-42
[13] S. Jung et al., "A process-aware hot/cold identification scheme for flash memory storage systems," in IEEE Trans. Consum. Electron. Vol. 56, no. 2, pp. 339-347, May 2010
[14] S. Kaxiras et al, “Cache decay exploiting generational behavior to reduce cache leakage power,” in 2001 ISCA
[15] S. Khan, Y. Tian, and D. A. Jimenez, “Sampling Dead Block Prediction for Last-Level Caches,” in 2010 MICRO, pp. 175-186
[16] M. Kharbutli and Y. Solihin, “Counter-Based Cache Replacement and Bypassing Algorithm”, in 2008 TC, pp. 433-447
[17] T. Lahiri et al., “Oracle database in-memory: a dual format in-memory database,” in 2015 ICDE, pp. 1253-1258
[18] P. A. Larson and J. Levandoski, “Modern main-memory database systems,” in VLDB Endowment, vol. 9, no. 13, 2016, pp.1609-1610
[19] S. Lee et al., “CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architectures,” in IEEE Trans. Comput., vol. 63, no. 9, pp.2187-2200, Sept. 2014.
[20] J. Lindstrom et al., “IBM solidDB: In-memory database optimized for extreme speed and availability,” IEEE Data Eng. Bull., pp. 14-20, 2013.
[21] Micron Technology, “SLC NAND,” [Online]. Available: https://www.micron.com/products/nand-flash/slc-nand/
[22] S. Mittal and J. S. Vetter, “A Survey of Software Techniques for Using Non-Volatile Memories for Storage and Main Memory Systems,” in IEEE Trans. Parallel Distrib. Syst., vol. 27, no. 5, pp.1537–1550, January 2016.
[23] J.C. Mogul et al., "Operating System Support for NVM+ DRAM Hybrid Main Memory," in HotOS 2009.
[24] K. Molka and G. Casale, “Contention-Aware Workload Placement for In-Memory Databases in Cloud Environments,” in ACM Trans. Modeling and Performance Evaluation of Comput. Syst., vol. 2, no.1,Oct.,2016.
[25] S. Naftaly, “Pin - A Dynamic Binary Instrumentation Tool,” [Online]. Available:https://software.intel.com/en-us/articles/pin-a-dynamic-binary-instrumentation-tool
[26] L. E. Ramos et al, “Page placement in hybrid memory systems,” in 2011 ICS, pp.85-95
[27] R. Salkhordeh and H. Asadi, “An Operating System level data migration scheme in hybrid DRAM-NVM memory architecture,” in DATE 2016, pp. 936-941
[28] SPEC CPU® 2006. https://www.spec.org/cpu2006/ Accessed: 2018-7-22
[29] D. A. Wood et al, “A Model for Estimating Trace-Sample Miss Ratios,” in 1991 SIGMETRICS, pp. 79-89
[30] Z. Wu et al., “APP-LRU: A new page replacement method for PCM/DRAM-based hybrid memory systems,” in NPC 2014, pp.84-95.
[31] H. Yoon et al., “Row buffer locality aware caching policies for hybrid memories,” in ICCD 2012, pp. 337-344