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研究生： 魏國修
Wei, Kuo-Hsiu
論文名稱： 銅化學機械研磨在奈米半導體積體電路製程之研究
Study of Nano-scale Copper Chemical Mechanical Planarization on Damascene Process for Semiconductor Integrated Circuits
指導教授： 劉全璞
Liu, Chuan-Pu
共同指導教授: 王英郎
Wang, Ying-Lang
學位類別： 博士
Doctor
系所名稱： 工學院 - 材料科學及工程學系
Department of Materials Science and Engineering
論文出版年： 2017
畢業學年度： 105
語文別： 英文
論文頁數： 71
中文關鍵詞： 銅化學機械研磨 、半導體製程 、研磨顆粒
外文關鍵詞： Copper CMP, Semiconductor manufacturing, Abrasive, Post-clean, Sponge, TMAH
相關次數： 點閱：98  下載：0 
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    • 隨著積體電路的進步，元件的導線 (interconnection) 已經演進至奈米等級 (nano-scale), 其主要的目的在於降低積體電路高度的元件積集度，及其產生的功率消耗與熱量，並大幅縮小其體積，以達成元件輕薄短小與高功能之可能。然在這奈米化的導線過程，製程技術更由原本的鋁銅導線與矽氧化物的介電材料，改變為銅導線與低介電常數 (low-K) 介電材料，以降低電阻-電容延遲時間效應 (RC delay time effect)。
    在銅導線的製造技術中，導入了鑲嵌技術 (damascene technology) 成為主流，主要是因銅的蝕刻技術較為困難。有別於傳統先將金屬圖案化再填入介電層，鑲嵌技術是將介電層的圖案先產生，再鑲嵌入銅金屬於導線圖案中。然這鑲嵌技術涉及三個重要製程技術，分別是銅擴散阻障層與導電功能的銅晶種層沈積 (deposition for barrier and seed layers)，銅電鍍 (copper electrodeposition, ECD)，銅化學機械研磨 (copper chemical mechanical planarization, CMP) 等技術。尤其是在銅化學機械研磨的製造技術，更是產生許多如技術整合效應、導線堆積精準、及製程缺陷等問題。因此本論文以主要討論銅化學機械研磨技術奈米化時，所需要解決的問題及製程缺陷，以達成奈米化導線的製程需求。
    在 CMP 研磨過程中，影響最終平坦化結果的因素，除了機台的設計之外，消耗材的選擇與設計亦扮演舉足輕重的角色。以研磨液為例，研磨顆粒的大小除了對於刮傷程度造成影響之外，本論文將討論不同大小的研磨顆粒對於研磨速率及去除機制上的影響。此外，針對研磨顆粒的殘留問題，本論文也將分別由重工 (Rework) 手法的設計及清潔機台內的刷子改質，進行探討，以期能減少對晶圓表面的影響。

    Semiconductor technology continues to advance in processing speed, power consumption, and cost per transistor. The well-publicized element of this advancement is shrinking feature size, now down to nanometer scale. The less talked about element, but just as important, is the material advancement. Copper has replaced aluminum as the primary interconnect material, to reduce electrical resistance for faster speed and low power consumption.
    Copper manufacturing had a late adoption due to the difficulty of copper etching. The key breakthrough was the introduction of damascene process, which bypasses the need to etch copper. The damascene process defined pattern by etching channels in dielectric material, then overfill the channels with copper, followed by polishing to remove excess copper outside of the channel. The polishing process is known as chemical mechanical planarization (CMP), and this manufacturing process need to overcome challenges with process integration, precise interconnection alignment, process defect management and so on. This thesis would focus on the issues and solutions of copper CMP manufacturing to enable the nano-scale interconnect.
    Copper CMP effectiveness is influenced by CMP equipment design, as well as design of consumable combination. For example, the design of consumable abrasive particles in slurry has direct impact on scratch generation, as well as removal rate and reaction mechanism. This thesis will examine the impact of abrasive particle size. In addition, this thesis will discuss the post-CMP abrasive removal by optimization of cleaner brush and rework methodology.

    Chinese Abstract I English Abstract II Acknowledgement IV Table of Contents V Table Caption VII Figure Caption VIII Chapter 1 Introduction 1 Chapter 2 Literature Review 3 2.1 The Development Background of Copper Application in Semiconductor Manufacture 3 2.2 Copper Damascene Process Development 9 2.3 Copper CMP Slurry 15 2.4 Post-Cleaning Defect in Copper CMP 16 2.5 Circular Ring Scratch Defect in Copper CMP 19 Chapter 3 Experiment Methods 21 3.1 Copper CMP Slurry Preparation 21 3.2 Post-Clean Condition in Copper CMP 22  Chapter 4 Influence of Abrasive Particle Size in Copper CMP 24 4.1 Result 24 4.2 Discussion 32 Chapter 5 Effect of Surfactant in Alkaline Copper CMP Post-Clean Chemical 34 5.1 Result 34 5.2 Discussion 42 Chapter 6 Circular Ring Scratch Formation in Post-CMP Cleaning 43 6.1 Result 43 6.2 Discussion 51 Chapter 7 Conclusions 53 Chapter 8 Suggestions for Future Study 55 Reference 56 Vita 65 Publication List 66

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