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研究生: 劉思安
Liu, Sih-An
論文名稱: 基於多位元組DFA並執行於GPU之正規表示式比對的加速演算法
Regular Expression Matching Acceleration Algorithm Using Multi-Byte DFA on GPU
指導教授: 張燕光
Chang, Yeim-Kuan
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2015
畢業學年度: 103
語文別: 英文
論文頁數: 61
中文關鍵詞: 深度封包檢測決定性有限狀態自動機GPUCUDA字串比對正規表示式
外文關鍵詞: Deep Packet Inspection, DFA, GPU, CUDA, Pattern Matching, Regular Expression
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  • 正規表示式比對在網路入侵偵測系統中扮演著不可或缺的角色,隨著網路流量快速地成長,正規表示式已經被廣泛運用在網路入侵偵測系統中,因為正規表示式的彈性與簡潔,近年來,繪圖處理器 (GPU) 經常被使用來加速正規表示式比對,經典的正規表示式比對方法有DFA,然而,DFA遭遇到狀態數爆炸的問題,它需要大量的記憶體空間。
    在這篇論文中,我們提出一個基於GPU的方法叫作MB-DFA,為了加速正規表示式比對他可以一次處理多個字元,並且解決了狀態數爆炸的問題,此外,我們也提出了一個壓縮的方案,可以壓縮default transition,基於我們的實驗結果,我們所提出的MB-DFA可以達到有效地降低記憶體的使用量,而且最好的效能在GPU可以達到83 Gbps.

    Regular expression matching plays an important role in Network Intrusion Detection System (NIDS). As the Internet traffic grows rapidly, regular expression have been widely used in NIDS due to its flexibility and conciseness. Recently, graphics processing unit (GPU) is often used to accelerate regular expression matching. The classical matching approach for regular expression matching uses deterministic finite automata (DFA). However, DFA suffers from the problem of state explosion because it needs a lot of memory space.
    In this thesis, we propose a GPU-based approach called Multi-Byte DFA (MB-DFA) which can process multiple characters per cycle in order to accelerate regular expression matching and solve the problem of state explosion. In addition, we also propose a compression scheme based on default transition. Our experimental results show that the proposed MB-DFA can achieve significant reductions in memory usage and the best performance of throughput is 83 Gbps on GPU.

    摘要 i Abstract ii Table of Contents iv List of Tables vi List of Figures vii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 2 Chapter 2 Related Work 3 2.1 String Matching Algorithm 3 2.1.1 Aho-Corasick algorithm 3 2.2 Regular Expression Matching Algorithm 6 2.2.1 Nondeterministic Finite Automaton (NFA) 6 2.2.2 Deterministic Finite Automaton (DFA) 9 2.2.3 Multi-Character NFA 11 2.3 GPU-based Algorithm 15 2.3.1 Parallel Failureless-AC algorithm 15 2.3.2 Multi-Byte Multi-Thread AC 17 2.3.3 Hierarchical Parallel Machine 21 Chapter 3 CUDA 23 3.1 Introduction 23 3.2 CUDA Programming Model 24 3.3 CUDA Hardware Model 28 Chapter 4 Proposed Scheme 31 4.1 Motivation 31 4.2 Overview 34 4.3 Detailed Construction Algorithm 37 4.4 Compression and Optimized Search 49 4.4.1 Default Transition 49 4.4.2 Optimized Search 49 4.4.3 Searching Phase 51 Chapter 5 Experimental Results 53 5.1 Simulation Environment 53 5.2 Pattern Sets and Input Traces 54 5.3 Memory Consumption 55 5.4 Evaluation of Various Input Traces 57 Chapter 6 Conclusion 59 Reference 60

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