本論文中我們首先探討兩種不同方式所製備的大面積二硫化鉬薄膜應用於元件，發現了藉由原子層沉積所製備的二硫化鉬薄膜所製作的元件比由濺鍍方式製備之薄膜來的較佳，原因為原子層沉積法之薄膜具有較佳的平整度及結晶性。之後我們開始二維材料電晶體優化工作，在接觸金屬方面，透過提高金屬鈦沉積溫度改善其結晶特性以及使用同為二維材料的金屬銻烯形成凡得瓦磊晶，逐步降低接觸電阻以改善元件特性。也利用薄膜再硫化的製程更進一步改善薄膜結晶性使元件特性持續提升。為了更進一步優化元件特性，透過改用單層二硫化鉬作為元件通道提升閘極對通道層的控制，在本文的元件優化工作將其開關電流比增加約385倍、場效電子遷移率增加約3735倍。接著依照相同的接觸電極概念運用到二硫化鉬光偵測器中，結果指出使用銻烯作為接觸金屬，其光電流高出兩個數量級，表明了二維材料凡得瓦磊晶的優勢在二維材料光電元件中可以有效提升光電流的收集。本論文也研究了二硫化鉬作為記憶體元件之應用，我們利用三層二硫化鉬薄膜以原子層蝕刻技術將上層之二硫化鉬孤立開來作為電荷儲存層，以防止帶電載子被施加的汲極電壓耗盡，其餘下層二硫化鉬作為電荷傳輸層。首先，我們透過電流遲滯曲線以及讀寫循環圖觀察到孤立二硫化鉬層越多電荷儲存的效果就越明顯，也進一步驗證載子是儲存於孤立二硫化鉬層的推論。也透過電流暫態圖觀察一次寫入/清除後1/0態維持的時效，觀察到1/0態讀取電流可維持達30分鐘。接著，透過改變寫入/清除時長觀察記憶體的操作速度，我們觀察到切換速度小於1秒，電流依舊跟得上切換速度呈現1/0狀態。最後，透過改變閘極操作偏壓觀察此記憶體閘極偏壓操作範圍。我們成功建構在只有幾個原子層厚度下具有1個電晶體0個電容器 (1T0C) 的動態隨機存取記憶體 (DRAM) 研究。

In this thesis, 2D material transistors are fabricated on wafer-scale MoS2 films prepared by the two-stage growth procedure. RF sputtering and the ALD are adopted to deposit Mo precursor on sapphire substrates before sulfurization. The higher field-effect mobility value of the MoS2 transistor fabricated by using ALD reveals that a uniform precursor distribution will help to form MoS2 films with improved crystallinity. After that, the work of optimizing device performance is for these issue of contact metals, the quality of films, the modulability of gate electrode. The best situation of device is using monolayer MoS2 as channel and antimonene as the contact metal. The device optimization work in this thesis increases its ON/OFF current ratio by about 385 times and the field-effect electron mobility by about 3735 times. The monolayer MoS2 film is used for photodetector application with different contact metals. The photocurrent of the photodetector using antimonene deposited at 75 ℃ as the contact metal is two orders of magnitude higher than that of the device deposited at room temperature with contact metal titanium, indicating the advantages of using 2D material van der Waals epitaxy can effectively improve the collection of photocurrent in 2D material optoelectronic devices. Next, we have demonstrated the application of multi-layer MoS2 as memory devices. Its operating mechanism and performance is observed by electrical measurements. we successfully constructed a dynamic random access memory (DRAM) with 1 transistor and 0 capacitors (1T0C) at only a few atomic layer thicknesses.

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