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研究生: 魯建廷
Lu, Chien-Ting
論文名稱: p型通道高電壓雙擴散金氧半場效電晶體其熱載子退化行為之研究
Hot-Carrier Induced Degradation of p-channel High Voltage Double-Diffused-Drain (DDD) MOSFET
指導教授: 陳志方
Chen, Jone-Fang
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2006
畢業學年度: 94
語文別: 英文
論文頁數: 65
中文關鍵詞: 雙擴散金氧半場效電晶體熱載子可靠度
外文關鍵詞: DDD MOSFET, reliability, hot-carrier
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  • 本篇論文主要的目的是探討p型通道高電壓雙擴散(DDD)金氧半場效電晶體之直流特性以及熱載子退化行為。文中將針對以下三個不同參數對於此高壓元件的影響做一個探討:(1)閘極到汲極寬度,(2)輕摻雜區域(PDD)之濃度,(3)閘極氧化層厚度。
    首先我們會對於元件的直流特性在各種不同結構和製程條件下做一個比較。接著對元件進行熱載子可靠度測試,觀察各情況下元件退化的程度。並且我們發現造成元件參數偏移最大的情況為閘極偏壓在最大閘極電流時,而electron trapping為最主要的影響機制。除此之外,我們也利用TCAD(Technical Computer Aided Design)模擬的結果來幫助分析熱載子退化的行為。

    In this thesis, the device characteristics and hot-carrier induced degradation of p-channel High-voltage (HV) Double-Diffused-Drain (DDD) MOSFETs are investigated.
    The effect of three different parameter conditions on DDD PMOSFETs discussed in my thesis, they are (1) Spacing S, (2) PDD dosage (3) Gate oxide thickness, respectively.
    First, we observe the device DC characteristics under different kinds of process conditions and structures. Then, hot-carrier stress is performed on devices with different conditions to see the degradation magnitude. And we find that the worst case stress condition occurred under Vg=Ig,peak at operating voltage, and electron trapping is the main mechanism. Besides, the results of TCAD (Technical Computer Aided Design) simulation are used to help us to analyze the hot-carrier induced degradation.

    Contents Chinese abstract …………………………………………………I English abstract …………………………………………………II Acknowledgements …………………………………………………III Content ……………………………………………………………IV Figure captions …………………………………………………VII Table captions ……………………………………………………XI Chapter 1 Introduction ……………………………………………1 1.1 HV MOSFET ………………………………………………………2 1.2 Device Description ……………………………………………3 1.2.1 Structure of Device ………………………………………3 1.2.2 Spacing S ……………………………………………………4 1.2.3 PDD dose ……………………………………………………5 1.2.4 Gate Oxide Thickness ……………………………………5 1.3 About the thesis ………………………………………………6 Chapter 2 Hot Carrier Behavior & Measurement of MOSFET …………………………………………………11 2.1 Hot-Carrier Effect In PMOS Transistors …………………12 2.1.1 Introduction ………………………………………………12 2.1.2 Model for Hot-Carrier Damage in PMOS ………………13 2.2 Measurement Setup & Condition ……………………………14 2.2.1 Device Parameter Measurement …………………………14 2.2.2 Threshold Voltage Extraction …………………………17 2.3 Stress Methodology Setup ……………………………………18 Chapter 3 Characteristics & Hot-Carrier Behavior of the DDD PMOSFET……………………………………………………25 3.1 Introduction ……………………………………………………26 3.2 Effect of Spacing S ……………………………………………26 3.3 Effect of PDD Dose ……………………………………………29 3.4 Summary ……………………………………………………………32 Chapter 4 Hot-Carrier Behavior of The DDD PMOSFET With Different Gate Oxide Thickness…………………………………………………50 4.1 Introduction ……………………………………………………51 4.2 Effect of Oxide Thickness …………………………………51 4.3 Summary …………………………………………………………53 Chapter 5 Conclusion and Future Work …………………………62 5.1 Conclusion and Future work …………………………………63 References ……………………………………………………………64

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