| 研究生: |
謝亞唐 Shieh, Ya-Tang |
|---|---|
| 論文名稱: |
IP為基之嵌入式SoC伺服運動控制系統設計與實現 IP-Based Embedded SoC Design and Implementation for Sevo Motion Control System |
| 指導教授: |
陳響亮
Chen, Shang-Liang |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 製造工程研究所 Institute of Manufacturing Engineering |
| 論文出版年: | 2003 |
| 畢業學年度: | 91 |
| 語文別: | 中文 |
| 論文頁數: | 93 |
| 中文關鍵詞: | 系統晶片 、智產 、嵌入式系統 、Nois |
| 外文關鍵詞: | SoC, IP, Nios, embedded system |
| 相關次數: | 點閱:94 下載:2 |
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隨著積體電路技術的日益進步,大閘數的晶片開發成功以及CPLD具有可重覆設計的功能,衍生出SoC的概念,所謂的SoC就是以使用智產(IP)的型式來建構一個完整功能的系統,因為SoC具有IP可重覆使用、可從新規劃,可攜性、外型輕巧、可
模組化、抗干擾性,重量輕等優點,因此許多學者紛紛投入研究。
有鑑於此,本研究提出以Fuzzy PID理論為基礎之IP配合伺服馬達運動控制系統IP,最後再與NIOS嵌入式處理器整合,建立IP-Based嵌入式SoC伺服運動控制系統。因此將對控制系統的核心Nios CPU IP、使用Fuzzy控制來模仿PID控制動作的FUZZY PID IP、儲存指令所需的FIFO IP、驅動伺服馬達所使用PWM IP、量測速度所需的Velocity Measuring IP、以及光編碼盤回授所需Feedback IP做深入的探討。
本文最後使用Altera公司所發展的軟核Embedded Processor發展板,將伺服馬達運動控制系統之各功能IP使用VHDL硬體描述語言設計電路,利用QuartusⅡ EDA tool將所設計的各功能IP進行模擬、合成與繞線,並探討各IP設計過程及模擬上的相關問題,最後將NIOS Processor與各功能IP整合,使用JTAG Port下載至Altera公司EP20K200EFC484-2X的硬體晶片,並使用C語言來撰寫程式碼,將執行檔Download到晶片,在On-Chip RAM中執行驅動NIOS Embedded Processor,最終設計出一個具有智慧型控制的IP-Based嵌入式SoC伺服馬達運動控制系統。
A SoC system is created by integrating several IPs (Intellectual Property) to achieve some special functions. The IPs in the SoC system are reusable, reconfigurable, and portable. These characters gives the SoC system several good points. For example, time to market and cost down. Therefore, the SoC design concept attracts many researchers in the recent years.
To design and implement an embedded IP-based SoC servo motor motion control system with intelligence is the aim of this research. There are five IPs are developed here for a servo motion control system. The intelligence is very important and essential for the practical applications of a servo motor motion control. Therefore, a fuzzy logic PID IP for a SoC servo motion control is the first IP to be designed and implemented. The IP for servo motor PWM technology is the second one. The third IP is the interface IP of the photo-encoder feedback interface circuit used in the motion control. The fourth IP is the measuring IP to measuring velocity of the sevo motor. The fifth IP is the FIFO IP. The FIFO IP is a data storage to model a queue so that the command data that comes in first will be read out first. The VHDL language is adopted to describe the hardware digital circuit of the developed IPs. The Quarters II EDA tool is used to integrate the developed IPs into a NIOS CPU. The simulation and placing & routing are also performed by using Quarters II EDA tool. The IP-based SoC servo motion control system is further download to an Altera APEX 20K200EFC484-2x chip to verify the correctness.
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