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研究生: 陳育瑞
Chen, Yu-juei
論文名稱: 即時多人臉偵測晶片實作
VLSI Implementation of a Real-Time Multi-Face Detection Processor
指導教授: 陳培殷
Chen, Pei-yin
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 中文
論文頁數: 53
中文關鍵詞: 人臉偵測影像插補器硬體實作
外文關鍵詞: face detection, image interpolator, hardware implementation
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  • 人臉偵測技術是影像處理應用中一個相當重要的話題。它已經廣泛地被使用於許多的應用,比如:人臉追蹤系統、自動門禁系統、銀行與海關監控系統等等。本論文提出一個改良型人臉偵測電路架構,我們改良傳統的人臉偵測演算法,採用縮小影像技術取代傳統放大矩形特徵大小的方式,達到放大子視窗大小的功能與降低暫存器使用的目的,同時利用固定點數運算取代浮點數運算,達到降低bit數的使用並增加運算速度。最後,我們應用層級交換技術,來大量節省硬體成本的消耗。實驗結果顯示,我們的方法在影像的偵測品質上跟OPENCV結果相當接近,而且我們提出的硬體架構,可以讓我們的電路在處理影像時更快且更有效率。根據合成模擬的結果,在 TSMC 0.18μm 製程下,我們的電路可以到達 40MHz的運作速度,在輸入影像大小640×480的情況下,人臉偵測電路的處理速度可達每秒40張影像。

    Face detection is a very important issue in the field of image processing. It has been used in many applications such as face tracking system, auto door-dog system, bank and custom surveillance system and so on. In this thesis, we propose a modified cascaded face detection circuit. Instead of scaling-up feature size, we use scaling-down image technique to get the effect of scaling-up sub-window and to avoid a lot of unnecessary registers. Besides, we use fixed-point operation to replace floating-point operation to reduce the hardware cost and achieve higher working speed. Finally, we adopt the stage switch technique to achieve lower hardware cost. Experiment results show that the performance of our design is almost the same as OPENCV. Furthermore, the proposed hardware architecture can implement face detection quickly and efficiently. According to our simulation, the design can operate at 40 MHz properly with the TSMC 0.18μm technology and process a video resolution of 640×480 at 40 fps in real time.

    中文摘要 I Abstract II 誌謝 III 目錄 IV 表目錄 VI 圖目錄 VII 第一章 緒論 1 1.1 研究背景及動機 1 1.2 研究方向 3 1.3 論文架構 3 第二章 Viola演算法與傳統影像縮放技術介紹 4 2.1 OPENCV的簡介 4 2.2 Viola人臉偵測演算法 4 2.3 傳統影像縮放技術 11 第三章 所提出的基於Viola演算法之人臉偵測系統 14 3.1 適合硬體實作Viola演算法實現方式 14 3.2 固定點實作與偵測準確度和硬體成本考量 16 3.3 矩形特徵與層疊分類器分析與硬體成本考量 19 3.4 改良型人臉偵測系統流程 24 3.5 硬體成本與複雜度的比較-層疊分類器 26 第四章 硬體架構及實作 28 4.1 硬體架構和運作流程 28 4.2 模組細節設計 31 4.2.1 影像緩衝區(Frame Buffer) 31 4.2.2 影像縮放控制單元(Scale Control Unit) 32 4.2.3 積分影像產生器與平方積分影像產生器 34 (Integral Image Generator & Square Integral Image Generator) 34 4.2.4 Line Buffer 35 4.2.5 子視窗暫存器(Sub-Window Register) 37 4.2.6 矩形特徵資料庫(Feature Bank) 37 4.2.7 層級分類處理器(Classifier Stage Process) 38 4.3 電路實作 44 第五章 實驗結果 45 第六章 結論 51 參考文獻 52

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