| 研究生: |
陳和良 Chen, Ho-Liang |
|---|---|
| 論文名稱: |
模數乘法演算法運用於智慧卡之研究 Study on Modular Multiplication Algorithms for Smart Card Applications |
| 指導教授: |
侯廷偉
Hou, Ting-Wei |
| 學位類別: |
碩士 Master |
| 系所名稱: |
工學院 - 工程科學系碩士在職專班 Department of Engineering Science (on the job class) |
| 論文出版年: | 2002 |
| 畢業學年度: | 90 |
| 語文別: | 中文 |
| 論文頁數: | 41 |
| 中文關鍵詞: | 模數乘法 、智慧卡 |
| 外文關鍵詞: | Modular Multiplication, Smart Card |
| 相關次數: | 點閱:92 下載:2 |
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目前大部份使用中的公開金鑰密碼系統中,最消耗時間及系統資源的部份就是modular exponentiation ,而其基礎則在於modular multiplication。本研究的目的在於儘可能地降低在smart card 上所須耗用的資源,特別是以可行的演算法來避免使用硬體除法器,藉此在標準微處理器上實作公開金鑰密碼演算法。
研究內容將詳細探討Montgomery modular multiplication algorithm在reduction過程中估算除法商數的演算法的實作方式。在考慮到以C++或Pascal等高階語言無法有效率地處理多重精確度的算術運算(主要是有關標準算術運算中carries 的取得及對記憶體的存取速度),實作中將以硬體描述語言來完成Montgomery algorithm的設計。
In most public-key crypto systems used today, the most time consuming part of these systems is the modular exponentiation. The base of this computation is the modular multiplication. Our study is to minimize the resources used in smart card. Hardware divisors will be prohibited if a comparable efficiency is obtained without it. Our study also focuses on the ability to implement modular multiplication algorithm on nearly standard processor.
This article first shows the implementation of the reduction of the Montgomery modular multiplication algorithm. On concerning the drawback on dealing with multiprecision arithmetic by high-level languages such as C++ or Pascal, the implementation will be finished by Verilog hardware description language on the design of Montgomery algorithm.
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