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研究生： 黃雅琪
Huang, Ya-Chi
論文名稱： 基於TCAD模擬評估之鰭式電晶體與橫向環繞式奈米片電晶體用於未來互補式場效應電晶體元件
TCAD-Based Assessment of FinFETs and Lateral Gate-All-Around Nanosheet FETs for Future CMOS Devices
指導教授： 江孟學
Chiang, Meng-Hsueh
王水進
Wang, Shui-Jinn
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年： 2022
畢業學年度： 110
語文別： 英文
論文頁數： 95
中文關鍵詞： 半導體製程 、元件模擬 、短通道效應 、鰭式電晶體 、環繞式閘極奈米線電晶體 、奈米片電晶體 、靜態隨機存取記憶體 、側向擴散金屬氧化物半導體 、高壓電晶體 、崩潰電壓
外文關鍵詞： TCAD simulation, short-channel effects, FinFET, GAA NWFET, NSFET, bulk inversion, SRAM, LDMOS, HV transistor, breakdown voltage
相關次數： 點閱：137  下載：25 
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    • 本論文提出鰭式電晶體、環繞式閘極奈米線電晶體與奈米片電晶體三種元件進行模擬與電性分析，並提出適合SoC應用具高密度(HD)、低電壓(LV)與高性能(HP)之多閘極元件靜態隨機存取記憶體(6T-SRAM)之面積設計，評估6T-SRAM高密度面積為0.008 μm2。
    首先本研究將針對一具成本優勢的實用型鰭式電晶體，以半導體元件模擬軟體Sentaurus TCAD提出模擬設計分析，於元件結構參數與尺寸參數遵循國際半導體技術指標於2028年之預測下，其在5奈米技術節點之電特性亦將與垂直堆疊奈米線電晶體進行比較，探討實用型鰭式電晶體於採用無摻雜(undoped)通道、傳統SiO2介電層、閘極和汲極/源極間的間隔層下通道存有underlap、以及不考慮晶格應變等情況下，於實際製作、減少成本與展現最佳特性上之優勢。
    本論文第二部分將聚焦於奈米片電晶體，針對不同通道寬度進行電特性之模擬分析。模擬通道長度於12奈米、技術節點於G40M16時，較寬奈米片的電晶體可以實現更大的驅動電流，然製程困難度較高；較窄奈米片可實現微縮元件之優勢，然將面臨驅動電流較小之問題。基於bulk inversion效應影響，傳統以每單位有效通道長度為基準衡量電晶體性能已不適用，而沿著奈米片寬度及其末端的bulk inversion，使環繞式閘極電晶體短通道效應控制的優勢受到挑戰。此部分之研究亦針對在相同平面面積(footprint)與製程元件結構整體高度下，比較分析鰭式電晶體與奈米片電晶體之電流、寄生電阻與電容、本質速度、fin pitch與footprint的關係，於成本和技術之間取得折衷，使FinFET持續成為延續CMOS技術一條更安全的途徑。
    本論文第三部分提出一種結合鰭片與平面通道的橫向二次擴散金氧半場效應電晶體，利用鰭式通道高度的優勢增加電流特性以及藉由平面通道減少很窄的fin寬度產生的串聯電阻。提升此一電晶體於I/O應用所需較高的崩潰電壓、較低的導通電阻與轉出較大電流等考量，於元件結構設計上，基於高壓元件的耐壓能力取決於閘極氧化層與漂移區寬度。本研究提出在漂移區與汲極間增加一可調式閘極區，利用增加可調式閘極電壓至2 V，提高電子之堆積提升元件之特性，與不加入可調式閘極區之導通電阻相比可下降約5倍，並分析驅動電流與可調式閘極電壓之關係，〖BV〗^2⁄R_(on_sp) 可提高約8倍，此設計可展現較佳高壓元件特性之元件結構。
    本論文亦進行多通道FinFET之實際研製，最後將針對模擬分析結果與實際製程所得FinFET之特性進行比較分析。

    The advanced technologies such as FinFETs, gate-all-around (GAA) NWFETs, and GAA NSFETs have emerged and established to resolve the short-channel effects (SCEs) issues. This work is focused on the simulations and analyses of multi-gate devices, and 6T-SRAM in terms of high density (HD), low voltage (LV), and high-performance (HP) operations for SoC applications. The HD SRAM cell area is 0.008 μm2.
    The performance of two-stacked GAAFET versus pragmatic FinFET architectures at the 5 nm technology node for HP and low operation power (LOP) applications and corresponding densities are investigated using the Sentaurus TCAD simulator. Simulation work conducted in this study takes into account the following assumptions: undoped fin UTB/channel, no high-κ dielectric, no lattice strain, and with gate-to-source/drain (G-S/D) underlap. All structural parameters of the devices under study are defined in reference to the International Roadmap for Devices and Systems (~5 nm node of the predecessor ITRS) at the G40M16 node for 2028.
    Furthermore, the device technology is advanced to the wide channel as GAA NSFET. The advantages of NSFET include a flexible sheet width and balance performance and drivability. The disadvantages include a complex fabrication process and severe parasitic effect. The conventional evaluation scheme to judge the performance of the transistor ‘per effective channel width’ is inappropriate due to pervasive bulk inversion. Bulk inversion, along the width of the nanosheet and at its ends, confuses the dependence of current on sheet/channel width and detracts from the assumed added benefit of SCE control in the GAA devices. FinFETs have simpler processing and discrete fins that are comparable (if not superior) in terms of the overall performance and device density. The electrostatics of lateral GAA nanosheet transistors and FinFETs of the same footprint are evaluated. It is worth noting that the trade-off between cost and technology must be ensured to extend the device scaling.
    Finally, HV transistors are used in I/O units for SoC applications. This study proposes an LDMOS that includes a combination of fins and planar channels with modulation gates. The introduction of fin channels helps enhance current drivability, and planar channels can help reduce large series resistance due to narrow fin widths. BV and R_on have a competitive relationship. The design of the modulation gate bias to 2 V can increase the electron accumulation obviously. Comparison between the hybrid FETs with and without the modulation gate, the R_on decreases about 5× and 〖BV〗^2⁄R_(on_sp) enhance about 8×. The variation in V_MOD versus 〖BV〗^2⁄R_(on_sp) for the design window is also clarified.
    In this study, the design and fabrication of multi-channel FinFETs were also studied, and the simulation results were compared with the experimental FinFETs characteristics.

    摘要 I Abstract III 致謝 V Contents VI Table Captions VIII Figure Captions IX Chapter 1 Introduction 1 1-1 Background and Transistor Scaling 1 1-2 Motivation 2 1-3 Overview of the Dissertation 7 Chapter 2 Challenges to the Evolution of Transistor Architectures 9 2-1 Architecture of Multi-gate MOSFETs 9 2-1-1 FinFET 9 2-1-2 Nanowire MOSFETs 13 2-1-3 Nanosheet FETs 14 2-1-4 Vertical GAA MOSFETs 15 2-2 TCAD Simulation Results 16 2-3 Six-Transistor Static Random Access Memory 20 Chapter 3 GAAFET Versus Pragmatic FinFET at the 5 nm Si-Based CMOS Technology Node 25 3-1 Challenges Associated with GAAFET and PFFET 25 3-2 Device Designs/Domains at the 5 nm Technology Node 26 3-3 Comparison of the Integration Densities 30 3-4 Simulation Results - Performance Comparison 31 3-5 Summary of GAAFET Versus PFFET 37 Chapter 4 TCAD-Based Assessment of the Lateral GAA Nanosheet Transistor for Future CMOS 38 4-1 FinFET and NSFET Beyond 3 nm 39 4-2 FinFET and NSFET Devices Simulations 40 4-3 Single-Sheet Device Results 42 4-4 Stacked-NSFET Results with Comparison to FinFET 47 4-5 Summarize the Lateral NSFET Issues and Lofty Expectations FinFET 52 Chapter 5 Simulation and Fabrication of Hybrid Fins and Planar Lateral Double-Diffused MOSFET 53 5-1 Hybrid Fin/Planar Type Channel Lateral Double-Diffused MOSFET 53 5-2 Simulated Structure of Hybrid FET with Modulation Gate 56 5-3 Process Flow and Fabrication Results of Hybrid FET with Modulation Gate 62 5-4 Measurement Results of Hybrid FET with Modulation Gate 66 5-5 Advantages of Hybrid FET with Modulation Gate 70 Chapter 6 Conclusions and Future Study 71 6-1 Conclusions 71 6-2 Scope of Future Research 73 References 75 Appendix 90 Publication List of Ya-Chi Huang 95

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