本論文以共濺鍍方式混合二氧化鋯與二氧化矽製備氧化矽鋯介電薄膜，探討不同沉積功率比例之材料特性，並應用於氧化銦鎵鋅薄膜電晶體以改善元件特性。
本研究主要分為兩個部分，第一部分為二氧化鋯與二氧化矽介電層之堆疊結構並應用於氧化銦鎵鋅薄膜電晶體，探究不同介電層界面品質於元件特性之影響；第二部分以共濺鍍製程技術結合二氧化鋯與二氧化矽製備氧化矽鋯介電層，藉調變沉積功率比例調整材料組成與特性，並進一步分析其應用於氧化銦鎵鋅薄膜電晶體之電特性。此外，為進一步提升元件特性，本論文亦討論以共濺鍍製程技術製備之氧化矽鋯介電層於經沉積後退火製程後，此薄膜之材料特性變化及其應用於元件上之電特性影響。
於第一部分研究中，旨在利用二氧化鋯與二氧化矽不同閘極介電層堆疊結構應用於氧化銦鎵鋅薄膜電晶體。藉由實驗結果得知，二氧化矽與氧化銦鎵鋅有較優異的界面品質與較少的界面缺陷，而堆疊介電層結構之沉積後退火亦對元件特性與遲滯效應有所改善。
於第二部分研究中，經由氧化矽鋯薄膜物性分析得知，摻入矽元素於二氧化鋯薄膜中可有效抑制二氧化鋯結晶形成，使氧化矽鋯有較平坦之薄膜表面。實驗結果顯示，經600 oC退火後亦維持非晶型態，且無擴散現象發生。而經由電特性分析得知，藉由調變二氧化矽之沉積功率，氧化矽鋯薄膜介電常數可獲得28.1至7.9範圍之調變，同時於相同等效氧化層厚度下亦有較低之漏電流。
氧化矽鋯介電層之氧化銦鎵鋅薄膜電晶體部分，由實驗結果顯示，摻入適量矽元素之氧化矽鋯有助於介電層與氧化銦鎵鋅間界面品質的改善，而過量之矽元素反而造成界面缺陷增加，將對於元件特性與遲滯效應造成負面影響。其中以矽與鋯比例為0.85與0.15之氧化矽鋯應用於IGZO-TFT時，可獲得最佳之電晶體特性。其元件電流開關比為1.24×108、次臨界擺幅為81 mV/dec、載子遷移率為51.70 cm2/V∙s、界面缺陷密度為7.05×1011 cm-2eV-1與遲滯效應之臨界電壓偏移為0.03 V。此一實驗結果已初步符合本論文於降低關閉電流、提升開關比、改善次臨限擺幅與降低界面缺陷之標的。
本論文成功於低溫環境下以共濺鍍製備氧化矽鋯閘極介電層並應用及改善氧化銦鎵鋅薄膜電晶體之界面品質與閘極控制能力。此氧化矽鋯薄膜可廣泛應用於各類低溫製程限制之基板，如玻璃基板和軟性塑膠基板，於未來顯示技術與軟性電子產品的應用深具潛力。

The use of co-sputtered zirconium silicon oxide (ZrxSi1-xO2) gate dielectrics to improve gate controllability of amorphous indium gallium zinc oxide (-IGZO) thin-film transistors (TFTs) is proposed and demonstrated. Through adjusting the sputtering power of the SiO2 target with that of the ZrO2 target kept at 100 W, a dielectric constant ranging from about 28.1 to 7.9 is obtained. Immunity of poly-structure formation of the ZrxSi1-xO2 dielectrics at evaluated temperatures (600 oC) is also examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric prepared at a power ratio of ZrO2:SiO2=100 W:50 W with PDA for 10 min in O2 at 600 oC could lead to a significantly improved device performance with a subthreshold swing (81 mV/dec) and a field effect mobility (51.70 cm2/V∙s).

[1] G. H. Heilmeier, L. A. Zanoni, and L. A. Barton, “Dynamic scattering: A new electrooptic effect in certain classes of nematic liquid crystals,” Proceedings of the IEEE, vol. 56, no. 7, pp. 1162-1171, 1968.
[2] T. P. Brody, J. A. Asars, and G. D. Dixon, “A 6 × 6 inch 20 lines-per-inch liquid-crystal display panel,” IEEE Transactions on Electron Devices, vol. 20, no. 11, pp. 995-1001, 1973.
[3] H. Kimura, T. Maeda, T. Tsunashima, T. Morita, H. Murata, S. Hirota, and H. Sato, “A 2.15 inch QCIF reflective color TFT-LCD with digital memory on glass (DMOG),” Proceedings of the SID, vol. 32, no. 1, pp. 268-270, 2001.
[4] 光電科技工業協進會(Photonics Technology & Industry Devlopment Association, PIDA), http://www.pida.org.tw/.
[5] S. B. Ogale, Thin films and heterostructures for oxide for oxide electronics, New York, NY: Springer, 2005.
[6] C. Jagadish and S. Pearton, Zinc oxide bulk, thin films and nanostructure, Oxford, UK: Elsevier, 2006.
[7] Ü. Özgür, Y. I. Alivov, C. Liu, A. Teke, M. A. Reshchikov, S. Doğan, V. Avrutin, S. J. Cho, and H. Morkoç, “A comprehensive review of ZnO materials and devices,” Journal of applied physics, vol. 98, no. 4, p. 041301, 2005.
[8] A. Janotti and C. G. Van de Walle, “Fundamentals of zinc oxide as a semiconductor,” Reports on Progress in Physics, vol. 72, no. 12, p. 126501, 2009.
[9] William Burton Pearson, Pierre Villars, Lauriston D. Calvert, Pearson's handbook of crystallographic data for intermetallic phases, American Society for Metals, 1985.
[10] D. J. Leary, J. O. Barnes, and A. G. Jordan, “Calculation of carrier concentration in polycrystalline films as a function of surface acceptor state density: application for ZnO gas sensors,” Journal of The Electrochemical Society, vol. 129, no. 6, pp. 1382-1386, 1982.
[11] G. Neumann, “On the defect structure of zinc-doped zinc oxide,” Physica Status Solidi (b), vol. 105, no. 2, pp. 605-612, 1981.
[12] Samanta, P. K. and Chaudhuri, P. R., “Substrate effect on morphology and photoluminescence from ZnO monopods and bipods”, Frontiers of Optoelectronics in China, vol. 4, no. 2, pp. 130-136, 2011.
[13] H. Hosono, “Ionic amorphous oxide semiconductors: Material design, carrier transport, and device application,” Journal of Non-Crystalline Solids, vol. 352, no. 9, pp. 851-858, 2006.
[14] T. Kamiya, K. Nomura, and H. Hosono, “Origins of high mobility and low operation voltage of amorphous oxide TFTs: Electronic structure, electron transport, defects and doping,” Journal of display Technology, vol. 5, no. 12, pp. 273-288, 2009.
[15] K. Nomura, A. Takagi, T. Kamiya, H. Ohta, M. Hirano, and H. Hosono, “Amorphous oxide semiconductors for high-performance flexible thin-film transistors,” Japanese Journal of Applied Physics, vol. 45, no. 5B, pp. 4303-4308, 2006.
[16] T. C. Fung, C. S. Chuang, K. Nomura, H. P. D. Shieh, H. Hosono, and J. Kanicki, “Photofield-effect in amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors,” Journal of Information Display, vol. 9, no. 4, pp. 21-29, 2008.
[17] M. Kim, J. H. Jeong, H. J. Lee, T. K. Ahn, H. S. Shin, J.-S. Park, Jae Kyeong Jeong, Y.-G. Mo, and H. D. Kim, “High mobility bottom gate InGaZnO thin film transistors with SiOx etch stopper,” Applied physics letters, vol. 90, no. 21, p. 212114, 2007.
[18] C.-S Chuang, T.-C Fung, B. G. Mullins, K. Nomura, T. Kamiya, H.-P. D. Shieh, H. Hosono, and J. Kanicki, “Photosensitivity of amorphous IGZO TFTs for active-matrix flat-panel displays,” SID Symposium Digest of Technical Papers, vol. 39, no. 1, pp. 1215-1218, 2008.
[19] N. C. Su, S. J. Wang, and A. Chin, “High-performance InGaZnO thin-film transistors using HfLaO gate dielectric” IEEE Electron Device Letters, vol. 30, no. 12, pp. 1317-1319, 2009.
[20] K. W. Lee, K. Y. Heo, S. H. Oh, A. Moujoud, G. H. Kim, and H. J. Kim, “Thin film transistors by solution-based indium gallium zinc oxide/carbon nanotubes blend,” Thin Solid Films, vol. 517, no. 14, pp. 4011-4014, 2009.
[21] J. Robertson and R. Wallace, “High-K materials and metal gates for CMOS applications,” Materials Science and Engineering: R: Reports, vol. 88, pp. 1-41, 2015.
[22] B. Cheng, M. C. Cao, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, J. M. Stork, M. Zeitzoff, and J. C. Woo, “The impact of high-κ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1537-1544, 1999.
[23] H.-L. Lu and D. W. Zhang, “Issues in High-k Gate Dielectrics and its Stack Interfaces,” High-k Gate Dielectrics for CMOS Technology, Weinheim, Germany, Wiley-VCH Verlag GmbH & Co. KGaA, pp. 31-59, 2012.
[24] H.-H. Tseng, The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies, Solid State Circuits Technologies, J. W. Swart, Ed., InTech, 2010.
[25] M.-T. Ho, Y. Wang, R. T. Brewer, L. S. Wielunski, Y. J. Chabal, N. Moumen, and M. Boleslawski, “In situ infrared spectroscopy of hafnium oxide growth on hydrogen-terminated silicon surfaces by atomic layer deposition,” Applied physics letters, vol. 87, no. 13, p. 133103, 2005.
[26] X. Zhao and D. Vanderbilt, “First-principles study of structural, vibrational, and lattice dielectric properties of hafnium oxide,” Physical Review B, vol. 65, no. 23, p. 233106, 2002.
[27] P. Taechakumput, S. Taylor, O. Buiu, R. Potter, and P. Chalker, “Optical and electrical characterization of hafnium oxide deposited by liquid injection atomic layer deposition,” Microelectronics Reliability, vol. 47, no. 4-5, pp. 825-829, 2007.
[28] V. Mikhelashvili and G. Eisenstein, “Effects of annealing conditions on optical and electrical characteristics of titanium dioxide films deposited by electron beam evaporation,” Applied physics letters, vol. 89, no. 6, pp. 3256-3269, 2001.
[29] H. Chakraborty and D. Misra, “Characterization of High-K Gate Dielectrics using MOS Capacitors,” International Journal of Scientific and Research Publications, vol. 3, no. 12, pp. 1-5, 2013.
[30] B. Lee, L. Kang, R. Nieh, W. Qi, and J. Lee, “Thermal stability and electrical characteristics of ultrathin hafnium oxide gate dielectric reoxidized with rapid thermal annealing,” Applied physics letters, vol. 76, no. 14, pp. 1926-1928, 2000.
[31] H. Kim, P. McIntyre, C. Chui, K. Saraswat, and S. Stemmer, “Engineering chemically abrupt high-k metal oxide/silicon interfaces using an oxygen-gettering metal overlayer,” Journal of Applied Physics, vol. 96, no. 6, pp. 3467-3472, 2004.
[32] S. Mohsenifar and M. H. Shahrokhabadi, “Gate Stack High-κ Materials for Si-Based MOSFETs Past, Present, and Futures”, Microelectronics and Solid State Electronics, vol.4, no. 1, pp. 12-24, 2015.
[33] S. M. Hu, “Stress-related problems in silicon technology,” Journal of Applied Physics, vol. 70, no. 6, pp. 53-80, 1991.
[34] T. M. Klein, D. Niu, W. S. Epling, W. Li, D. M. Maher, C. C. Hobbs, R. I. Hegde, I. J. R. Baumvol, and G. N. Parsons, “Evidence of aluminum silicate formation during chemical vapor deposition on amorphous Al2O3 thin films on Si (100),” Applied physics letters, vol. 75, no. 25, pp. 4001-4003, 1999.
[35] H. F. Luan, S. J. Lee, S. C. Song, Y. L. Mao, Y. Senzaki, D. Roverts, and D. L. Kwong, “High quality Ta2O5 gate dielectrics with Tox, eq less than 10Å,” IEDM Technical Digest. International Electron Devices Meeting, pp. 141-142, 1999.
[36] K. J. Hubbard and D. G. Schlom, “Thermodynamic stability of binary oxides in contact with silicon,” Journal of Materials Research, vol. 11, no. 11, pp. 2757-2776, 1996.
[37] R. Puthenkovilakam, E. A. Carter, and J. P. Chang, “First-principles exploration of alternative gate dielectrics: Electronic structure of ZrO2/Si and ZrSiO4/Si interfaces,” Physical Review B, vol. 69, no. 15, p. 155329, 2004.
[38] C. B. Jeon, S. H. Kong, and J. Y. Kim, “Characteristics of Zirconium-Silicate Films Prepared by Using Di erent Co-Sputtering Methods,” Journal of the Korean Physical Society, vol. 42, no. 2, pp. 267-271, 2003.
[39] B. C. Wang, S. L. Wu, Y. Y. Lu, S. J. Chang, J. F. Chen, S. C. Tsai, C. H. Hsu, C. W. Yang, C. G. Chen, O. Cheng, and P. C. Huang, “Comparison of the Trap Behavior Between ZrO2 and HfO2 Gate Stack nMOSFETs by 1/f Noise and Random Telegraph Noise,” IEEE Electron Device Letters, vol. 34, no. 2, pp. 151-153, 2013.
[40] S. C. Tsai, S. L. Wu, B. C. Wang, S. J. Chang, C. H. Hsu, C. W. Yang, C. M. Lai, C. W. Hsu, O. Cheng, Po C. Huang, and J. F. Chen, “Low-Frequency Noise Characteristics for Various ZrO2-Added HfO2-Based 28-nm High-k/Metal-Gate nMOSFETs,” IEEE Electron Device Letters, vol. 34, no.7, pp. 834-836, 2013.
[41] S. Kim, M. H. Ham, B. Y. Oh, H. J. Kim, and J. M. Myoung, ”High-κ TixSi1-xO2 thin films prepared by co-sputtering method,” Microelectronic Engineering, vol. 85, pp. 100-103, 2008.
[42] D. Cho, S. Woo, J. Yang, D. Lee, Y. Lim, D. Kim, S. Park, and M. Yi, “High Performance Thin Film Transistor with HfSiOx Dielectric Fabricated at Room Temperature RF-Magnetron Sputtering,” Electronic Materials Letters, vol. 9, no. 4, pp. 381-384, 2013.
[43] J. C. Park, I.-T. Cho, E.-S. Cho, D. H. Kim, C.-Y. Jeong, and H.-I. Kwon, “Comparative Study of ZrO2 and HfO2 as a High-κ Dielectric for Amorphous InGaZnO Thin Film Transistors,” Journal of Nanoelectronics and Optoelectronics, vol. 9, pp. 67-70, 2014.
[44] S. Mohsenifar and M. H. Shahrokhabadi, ”Gate Stack High-κ Materials for Si-Based MOSFETs Past, Present, and Futures,” Microelectronics and Solid State Electronics, vol. 4, no. 1, pp. 12-24, 2015.
[45] W. P. Zhang, S. Chen, S. B. Qian, and S. J. Ding, “Effects of thermal annealing on the electrical characteristics of In-Ga-Zn-O thin-film transistors with Al2O3 gate dielectric,” Semiconductor Science and Technology, vol. 30, no. 1, p. 015003, 2015.
[46] X. Ding, J. Zhang, H. Zhang, H. Ding, C. Huang, J. Li, W. Shi, X. Jiang, and Z. Zhang, “ZrO2 insulator modified by a thin Al2O3 film to enhance the performanceof InGaZnO thin-film transistor,” Microelectronics Reliability, vol.54, no. 11, pp. 2401-2405, 2014.
[47] R. Mahapatra, J.-H. Lee, S. Maikap, G. S. Kar, A. Dhar, N.-M. Hwang, D.-Y. Kim, B. K. Mathur, and S. K. Ray, “Electrical and interfacial characteristics of ultrathin ZrO2 gate dielectrics on strain compensated SiGeC/Si heterostructure,” Applied Physics Letters, vol. 82, no. 14, pp. 2320-2322, 2003.
[48] D. Fischer and A. Kersch, “The effect of dopants on the dielectric constant of HfO2 and ZrO2 from first principles,” Applied Physics Letters, vol. 92, no. 1, p. 12908, 2008.
[49] H. C. Chiu. H. C. Wang, C. K. Lin, C. W. Chiu, J. S. Fu, K. P. Hsueh, and F. T. Chien, “Low Frequency Noise Analysis of Top-Gate MgZnO Thin-Film Transistor with High-k ZrO2 Gate Insulator,” Electrochemical and Solid-State Letters, vol. 14, no. 9, pp. H385-H388, 2011.
[50] B. E. Deal, “Standardized terminology for oxide charges associated with thermally oxidized silicon,” IEEE Trans. Electron Devices, vol. 127, no. 4, pp. 979-981, 1980.
[51] S. M. Sze and M. K. Lee, Semiconductor Devices Physics and Technology, 3rd edition, Hoboken, N.J., Wiley, pp. 238-239, 2012.
[52] D. K. Schroder, Semiconductor material and device characterization, 2nd edition, Wiley, New York, pp. 367-369, 1998.
[53] M. Zambuto, Semiconductor Devices, McGraw-Hill Book Company, Ch. 9, pp. 284-332, 1989.
[54] A. Goetzberger, E. Klausmann, and M. J. Schulz, “Interface states on semiconductor/insulator interface surfaces,” Critical Reviews in Solid State and Material Sciences, vol. 6, no. 1, pp. 1-43, 1976.
[55] M. Koyama, Y. Kamimuta, T. Ino, A. Nishiyama, A. Kaneko, S. Inumiya, K. Eguchi, and M. Takayanagi, “Careful examination on the asymmetric VFB shift problem for poly-Si/HfSiON gate stack and its solution by the Hf concentration control in the dielectric near the poly-Si interface with small EOT expense,” Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, pp. 499-502, 2004.
[56] D. A. Neamen, Semiconductor Physics and Devices: Basic Principles, 4th Edition, McGraw-Hil Higher Education, New York, NY, p. 718, 2012.
[57] T. C. Fung, G. Baek, and J. Kanicki, “Low frequency noise in long channel amorphous In-Ga-Zn-O thin film transistors,” Journal of Applied Physics, vol. 108, no.7, p. 074518, 2010.
[58] A. D. Van Rheenen, G. Bosman, and R. J. J. Zijlstra, “Low frequency noise measurements as a tool to analyze deep-level impurities in semiconductor devices,” Solid-State Electronics, vol. 30, no. 3, pp. 259-265, 1987.
[59] J. Rhayem, D. Rigaud, M. Valenza, N. Szydlo, and H. Lebrun. “1/f noise modeling in long channel amorphous silicon thin film transistors,” Journal of Applied Physics, vol. 87, no. 4, pp. 1983-1989, 2000.
[60] A. Merchaa, L. Pichon, R. Carin, K. Mourgues, and O. Bonnaud, “Grain boundary trap passivation in polysilicon thin film transistor investigated by low frequency noise,” Thin Solid Films, vol. 383, no. 1, pp. 303-306, 2001.
[61] A. Bonfiglietti, A. Valletta, L. Mariucci, A. Pecora, and G. Fortunato, “Noise performance of polycrystalline silicon thin-film transistors made by sequential lateral solidification,” Applied Physics Letters, vol. 82, no. 16, pp. 2709-2711, 2003.
[62] L. X. Qian, X. Z. Liu, C. Y. Han, and P. T. Lai, “Improved Performance of Amorphous InGaZnO Thin-Film Transistor With Ta2O5 Gate Dielectric by Using La Incorporation”, IEEE Transactions on Device and Materials Reliability, vol. 14, no. 4, pp. 1056-1060, 2014.
[63] J. C. Park, S. I. Kim, C. J. Kim, S. Kim, D. H. Kim, I. T. Cho, and H. I. Kwon, “Impact of High-k HfO2 Dielectric on the Low-Frequency Noise Behaviors in Amorphous InGaZnO Thin Film Transistors,” Japanese Journal of Applied Physics, vol 49, no. 10R, p. 100205, 2010.
[64] S. D. Brotherton, Introduction to Thin Film Transistors: Physics and Technology of TFTs, TFT Consultant, Forest Row, E. Sussex, UK, pp. 63-64, 2013.
[65] S. Jun, C. Jo, H. Bae, H. Choi, D. H. Kim, and D. M. Kim, “Unified subthreshold coupling factor technique for surface potential and subgap density-of-states in amorphous thin film transistors,” IEEE Electron Device Letters, vol. 34, no. 5, pp. 641-643, 2013.
[66] J. H. Park, K. Jeon, S. Lee, S. Kim, S. Kim, I. Song, C. J. Kim, J. Park, Y. Park, D. M. Kim, and D. H. Kim, “Extraction of density of states in amorphous GaInZnO thin-film transistors by combining an optical charge pumping and capacitance–voltage characteristics,” IEEE Electron Device Letters, vol. 29, no.12, pp. 1292-1295, 2008.
[67] S. C. Sun and J. D. Plummer, “Electron Mobility in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces,” IEEE Journal of Solid-State Circuits, vol. 15, no. 4, pp. 562-573, 1980.
[68] H.S. Wong, M.H. White, T.J. Krutsick, and R.V. Booth, “Modeling of Transconductance Degradation and Extraction of Threshold Voltage in Thin Oxide MOSFET’s,” Solid-State Electronics, vol. 30, no. 9, pp. 953-968, 1987.
[69] H.G. Lee, S.Y. Oh, and G. Fuller, “A Simple and Accurate Method to Measure the Threshold Voltage of an Enhancement-Mode MOSFET,” IEEE Transactions on Electron Devices, vol. 29, no. 2, pp. 346-348, 1982.
[70] S. Jain, “Measurement of Threshold Voltage and Channel Length of Submicron MOSFETs,” IEE Proceedings I-Solid-State and Electron Devices, vol. 135, no. 6, pp. 162-164, Dec. 1988.
[71] M. Tsuno, M. Suga, M. Tanaka, K. Shibahara, M. Miura-Mattausch, and M. Hirose, “Physically-Based Threshold Voltage Determination for MOSFET’s of All Gate Lengths,” IEEE transactions on electron devices, vol. 46, no. 7, pp. 1429-1434, 1999.
[72] F.M. Klaassen and W. Hes, “On the Temperature Coefficient of the MOSFET Threshold Voltage,” Solid-State Electronics, vol. 29, no. 8, pp. 787-789, 1986.
[73] S. J. Yun, J. B. Koo, J. W. Lim, and S. H. Kim, “Pentacene-Thin Film Transistors with ZrO2 Gate Dielectric Layers Deposited by Plasma-Enhanced Atomic Layer Deposition,” Electrochemical and Solid-state Letters, vol. 10, no. 3, pp. H90-H93, 2007.
[74] S. C. Sun and J. D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces,” IEEE Trans. Electron Devices, vol. ED-27, no. 8, pp. 1497-1508, 1980.
[75] John F. Wager, Douglas A. Keszler, and Rick E. Presley, Transparent Electronics, Springer, New York, pp. 140-142, 2008.
[76] Xinyuan Zhao and David Vanderbilt, “Phonons and lattice dielectric properties of zirconia,” Physical Review B, vol. 65, no. 7, p. 075105, 2002.
[77] L.X. Qian and P. T. Lai, “A study on the electrical characteristics of InGaZnO thin-film transistor with HfLaO gate dielectric annealed in different gases”, Microelectronics Reliability, vol. 54, no. 11, pp. 2396-2400, 2014.
[78] Research Center for Magnetic and Spintronic Materials (CMSM), Schematic of Magnetron sputtering, http://www.nims.go.jp/mmu/tutorials/sputtering.html.
[79] 台灣鎧柏科技有限公司(AdNaNo), 磁控濺鍍工作原理, http://www.dualsignal.com.tw/30913255112866623556magnetron-sputtering.html.
[80] J.-L. Her, F.-H. Chen, W.-C. Li, and T.-M. Pan, “High-Performance Amorphous InGaZnO Thin-Film Transistors With HfO2/Lu2O3/HfO2 Sandwich Gate Dielectrics,” IEEE Transactions on Electron Devices, vol. 62, no. 5, pp. 1659-1662, 2015.
[81] J. Song, C. Han, and P. T. Lai, “Comparative Study of Nb2O5, NbLaO, and La2O3 as Gate Dielectric of InGaZnO Thin-Film Transistor,” IEEE Transactions on Electron Devices, vol. 63, no. 5, pp. 1928-1933, 2016.