隨著製程的進步晶片越做越小，電路中單位面積可以容納更多電晶體，但也因此電路的功率密度(Power Density)也越來越高，溫度也越來越高，除了增加設計能本，也降低電路的可靠性。為了解決此問題處理器逐漸由單核心往多核心發展，單核心處理器為晶片中有一個高效能核心，多核心處理器內雖然其各核心效能較低，但卻多顆核心可以分散計算資源，因此其最大好處在於晶片上的熱能不會過於集中而造成溫度過高。

多核心處理器設計上有兩項非常重要的問題，分別是Process Variation (PV) 及Negative Bias Temperature Instability (NBTI)。Process Variation是由於製程十分精細而很難精確控制造成電晶體的參數不同進而影響到電路運作，造成電晶體間Leakage Power、Frequency及Temperature的差異，最終會由於Leakage Power過高或者Frequency太低而降低晶片的良率。NBTI則是由於在電路運作過程當中電場破壞矽氫鍵結而產生Interface Trap進而使Threshold Voltage逐漸提高，造成電路運作速度退化，電路最終因效能太低無法正常運作。

本研究中提出一套流程以分析NBTI對功率及溫度限制之多核心處理器的影響。首先介紹如何模擬多核心處理器，並考慮Process Variation的影響。之後透過NBTI model來分析NBTI effect在未來10年內對於多核心處理器效能的影響，最後透過Adaptive Voltage Scaling(AVS)、Adaptive Body Biasing (ABB)、Core Rotation以及Schedule Voltage Scaling各種技術來改善NBTI effect所帶來的效能老化。

本研究分析中發現如果同時考慮Process Variation與NBTI對multicore processor的影響，電路在10年以後將會減少30%的效能，由此可知問題的重要性。透過Adaptive Voltage Scaling的分析指出只要提高16.7%的VDD就可以保證電路在未來10年可以正常的運作，使用Core Rotation可以提高4% ~ 7%的效能改善， Schedule Voltage Scaling則是可以在電路初期使用較低的電壓，如此不僅電路初期使用中的耗能較少，也由於溫度較低而減緩電路老化。

Along with the advent of advanced process technology and shrinking transistor sizes, the power density in chips has increased exponentially. High power density, which normally produces high temperature in a chip, will either increase the chip design costs or reduce system reliability. Therefore, it poses a serious threat to circuit design. In order to mitigate the problem, the development of microprocessors has changed from a single-core to a multicore design. Rather than putting a high performance core in a chip, the multicore processor integrates numerous less powerful cores in the chip. The multicore processor can distribute workload into various cores and hence reduce the power density.

Multicore processors have two major issues: Process Variation (PV) and Negative Body Bias Instability (NBTI). PV is caused by the disability to precisely control the fabrication process in a nanometer technology. PV results in parameter variances in transistors. The different parameters in the transistors directly affect the circuits in such ways as leakage power variations and operating frequency and temperature variations. The difference in parameters lowers the yields because leakage power is too high, or frequency is too low. Meanwhile, NBTI is caused by the dissociation of silicon-hydrogen bonds due to high electrical fields. Interface traps are generated, increasing the threshold voltage. Finally, the circuits may fail if they are unable to meet the timing requirements.

In this thesis, we propose a flow to analyze the impact of the NBTI effect for multicore processors. In this flow, it simulates a multicore processor and takes process variation into consideration. The flow applies the long term NBTI model to each core to analyze the performance degradation due to the NBTI effect over a ten year period. Finally, the flow uses Adaptive Voltage Scaling (AVS), Adaptive Body Biasing (ABB), Core Rotation and Schedule Voltage Scaling (SVS) to mitigate the performance degradation due to the NBTI effect.

After we introduce the flow, we use the flow to investigate the throughput impact of process variation and NBTI on power and thermal-constraint multicore processors. The results show up to 30% degradation when both process variation and NBIT are considered. An increase of 16.7% in supply voltage can guarantee the operation of the circuit over ten years. The Core Rotation technique can improve the throughput by 4% ~ 7%. Finally, schedule voltage-scaling can provide lower supply voltage and lower power consumption in the early stages, which leads to lower temperature and a reduction in the NBTI effect.

[1] G. Taylor, "Energy efficient circuit design and the future of power delivery," presented at the EPEPS, 2009.
[2] J. W. Tschanz, et al., "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," Solid-State Circuits, IEEE Journal of, vol. 37, pp. 1396-1402, 2002.
[3] N. Kimizuka, et al., "The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling," in VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on, 1999, pp. 73-74.
[4] S. Borkar, et al., "Parameter variations and impact on circuits and microarchitecture," presented at the Proceedings of the 40th annual Design Automation Conference, Anaheim, CA, USA, 2003.
[5] S. R. Sarangi, et al., "VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects," Semiconductor Manufacturing, IEEE Transactions on, vol. 21, pp. 3-13, 2008.
[6] R. Vattikonda, et al., "Modeling and minimization of PMOS NBTI effect for robust nanometer design," in Design Automation Conference, 2006 43rd ACM/IEEE, 2006, pp. 1047-1052.
[7] S. Bhardwaj, et al., "Predictive Modeling of the NBTI Effect for Reliable Design," in Custom Integrated Circuits Conference, 2006. CICC '06. IEEE, 2006, pp. 189-192.
[8] M. Basoglu, et al., "NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime," presented at the Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design, Austin, Texas, USA, 2010.
[9] L. Zhang and R. P. Dick, "Scheduled voltage scaling for increasing lifetime in the presence of NBTI," presented at the Proceedings of the 2009 Asia and South Pacific Design Automation Conference, Yokohama, Japan, 2009.
[10] Z. Qi and M. R. Stan, "NBTI resilient circuits using adaptive body biasing," presented at the Proceedings of the 18th ACM Great Lakes symposium on VLSI, Orlando, Florida, USA, 2008.
[11] M. DeBole, et al., "A framework for estimating NBTI degradation of microarchitectural components," presented at the Asia and South Pacific Design Automation Conference. ASP-DAC 2009., 2009.
[12] J. Lee, et al., "Analyzing impact of multiple ABB and AVS domains on throughput of power and thermal-constrained multi-core processors," presented at the the 2010 Asia and South Pacific Design Automation Conference, Taipei, Taiwan, 2010.
[13] J. Lee and N. S. Kim, "Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating," presented at the 46th Annual Design Automation Conference, San Francisco, California, 2009.
[14] Digital Integrated Circuits.
[15] Available: http://leg.ufpr.br/geoR/
[16] M. D. Hill and M. R. Marty, "Amdahl's Law in the Multicore Era," Computer, vol. 41, pp. 33-38, 2008.
[17] Predictive Technology Model (PTM) and NBTI Model. Available: http://www.eas.asu.edu/~ptm