本論文目標為提供電阻式記憶體在計算應用之研究，包含基於電阻式記憶體胞的陣列與類神經網路單元的設計、製程和分析。此非揮發性記憶體元件內部電阻的切換特性及調變動態為電阻式記憶體胞的核心，也是本研究相當重要的基礎。此研究中的重要實驗包含兩種形式的記憶體元件製程，基於氧空缺傳導的電阻式記憶體元件製程，與主動電極構成之基於金屬導電橋傳導的電阻式記憶體元件製程，並針對皆以同樣雙層異質介電材料構成之電阻切換層（氧化鉿/氧化鋁）的前述兩製程所製造之元件，進行量測分析，展現出非線性電流-電壓特性，且各記憶體胞在陣列中的操作互相不干擾，可獨立寫入/讀取，其中特性包含多電阻狀態的可調變特性，無論是在直流操作抑或脈衝操作，且前述兩種電阻式記憶體元件皆然，差別只在於各有其調變方法。關於運算方法的研究，進行在兩種新型的記憶體胞複合網路單元，分別是電阻式記憶體複合邏輯，及電阻式記憶體環形單元，皆利用電阻式記憶體其非揮發性、高速反應（小於一百奈秒）、脈衝可調變特性，將電阻式記憶體整合於類神經網路單元。電阻式記憶體不再僅被視為單個儲存點，而被視為另一新概念，作為類神經網路的突觸，利用多阻態可調變性，被應用在類神經網路中成為調控路徑權重的突觸元件，提供類神經運算、乘數累加運算及電阻式記憶體的單元於運算應用的操作方法及實現，期望從元件工程視角為電阻式記憶體整合於未來高效能運算提供可能性。

The objective of this research is to explore the role of resistive random access memory (RRAM) as the protagonist in computing. Different designs of RRAM-based array circuits and networks are implemented and discussed in detail in this thesis. Starting from the essences of this resistive switching non-volatile memory (NVM) cell fabricated in two representative types: oxygen-vacancy type oxygen-vacancy RRAM (OxRRAM) and metallic type conductive-bridge RRAM (CBRAM), with in-depth looks on their diverse resistive-switching mechanisms from measured experimental results, and performance as memory devices, to see prospects on integrations of RRAM with same bilayer stack of transition metal oxide (TMO) Al2O3/HfO2 as resistive switching layer for OxRRAM (top electrode, TE: Pt/Ti, bottom electrode, BE: Pt) and CBRAM (active electrode, AE: Cu, counter electrode, CE: Al). The bilayer structure results in nonlinear I-V for higher capacity of selector-less cell integration, and is proved to be anti-crosstalk in forming/set/reset/read operation on fabricated array samples, capable of being modulated into gradual states with different scheme in OxRRAM and CBRAM, as a result of different I-V behaviors in dc and transient waveforms in ac. The computing strategies are experimented with unprecedented 2 designs as RRAM-based network circuits, a RRAM composite logic unit (RCLU) and a composite ring unit (RCRU), in which exploit the advantages of non-volatility, responsive switching (<100ns), and pulse-modulable multiple-state, in this resistive-switching device, supporting a new idea of utilizing RRAM, not only as a “storage node” anymore, but becoming a new “weight” update synaptic element on path of a network circuit for neuromorphic (brain-like learning) and multiply-accumulate (MAC) computation, and practical device implementations of RRAM-based unit-wise network element are demonstrated in this thesis. This thesis is to ultimately provide an insight on RRAM as a computing element in the new era of high-performance computation.

[1] I. G. Baek, D. C. Kim, M. J. Lee, H. J. Kim, E. K. Yim, M. S. Lee, J. E. Lee, S. E. Ahn, S. Seo, J. H. Lee, J. C. Park, Y. K. Cha, S. O. Park, H. S. Kim, I. K. Yoo, U. Chung, J. T. Moon, and B. I. Ryu, "Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application," in IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest., 2005, pp. 750-753.
[2] M. Bocquet, T. Hirztlin, J. O. Klein, E. Nowak, E. Vianello, J. M. Portal, and D. Querlioz, "In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks," in 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 20.6.1-20.6.4.
[3] D. J. Wouters, L. Brackmann, A. Jafari, C. Bengel, M. Mayahinia, R. Waser, S. Menzel, and M. Tahoori, "Reliability of Computing-In-Memory Concepts Based on Memristive Arrays," in 2022 International Electron Devices Meeting (IEDM), 2022, pp. 5.3.1-5.3.4.
[4] T. Dalgaty, N. Castellani, C. Turck, K.-E. Harabi, D. Querlioz, and E. Vianello, "In situ learning using intrinsic memristor variability via Markov chain Monte Carlo sampling," Nature Electronics, vol. 4, no. 2, pp. 151-161, 2021.
[5] T. Babina, A. Fedyk, A. He, and J. Hodson, "Artificial intelligence, firm growth, and product innovation," Journal of Financial Economics, vol. 151, p. 103745, 2024.
[6] L. Chua, "Memristor-The missing circuit element," IEEE Transactions on Circuit Theory, vol. 18, no. 5, pp. 507-519, 1971.
[7] D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, "The missing memristor found," Nature, vol. 453, no. 7191, pp. 80-3, 2008.
[8] J. J. Yang, D. B. Strukov, and D. R. Stewart, "Memristive devices for computing," Nature Nanotechnology, vol. 8, no. 1, pp. 13-24, 2013.
[9] A. Siemon, R. Drabinski, M. J. Schultis, X. Hu, E. Linn, A. Heittmann, R. Waser, D. Querlioz, S. Menzel, and J. S. Friedman, "Stateful Three-Input Logic with Memristive Switches," Sci Rep, vol. 9, no. 1, p. 14618, 2019.
[10] J. J. Yang, M. D. Pickett, X. Li, D. A. A. Ohlberg, D. R. Stewart, and R. S. Williams, "Memristive switching mechanism for metal/oxide/metal nanodevices," Nature Nanotechnology, vol. 3, no. 7, pp. 429-433, 2008.
[11] G. Bersuker, D. C. Gilmer, D. Veksler, J. Yum, H. Park, S. Lian, L. Vandelli, A. Padovani, L. Larcher, K. McKenna, A. Shluger, V. Iglesias, M. Porti, M. Nafría, W. Taylor, P. D. Kirsch, and R. Jammy, "Metal oxide RRAM switching mechanism based on conductive filament microscopic properties," in 2010 International Electron Devices Meeting, 2010, pp. 19.6.1-19.6.4.
[12] Y. Li, M. Zhang, S. Long, J. Teng, Q. Liu, H. Lv, E. Miranda, J. Sune, and M. Liu, "Investigation on the Conductive Filament Growth Dynamics in Resistive Switching Memory via a Universal Monte Carlo Simulator," Sci Rep, vol. 7, no. 1, p. 11204, 2017.
[13] W. Wu, H. Wu, B. Gao, P. Yao, X. Zhang, X. Peng, S. Yu, and H. Qian, "A Methodology to Improve Linearity of Analog RRAM for Neuromorphic Computing," in 2018 IEEE Symposium on VLSI Technology, 2018, pp. 103-104.
[14] S. A. Chekol, S. Menzel, R. W. Ahmad, R. Waser, and S. Hoffmann‐Eifert, "Effect of the Threshold Kinetics on the Filament Relaxation Behavior of Ag‐Based Diffusive Memristors," Advanced Functional Materials, vol. 32, no. 15, 2021.
[15] W. Wang, M. Wang, E. Ambrosi, A. Bricalli, M. Laudato, Z. Sun, X. Chen, and D. Ielmini, "Surface diffusion-limited lifetime of silver and copper nanofilaments in resistive switching devices," Nat Commun, vol. 10, no. 1, p. 81, 2019.
[16] U. Celano, G. Giammaria, L. Goux, A. Belmonte, M. Jurczak, and W. Vandervorst, "Nanoscopic structural rearrangements of the Cu-filament in conductive-bridge memories," Nanoscale, vol. 8, no. 29, pp. 13915-23, 2016.
[17] W. Banerjee and H. Hwang, "Understanding of Selector‐Less 1S1R Type Cu‐Based CBRAM Devices by Controlling Sub‐Quantum Filament," Advanced Electronic Materials, vol. 6, no. 9, 2020.
[18] Y.-J. Choi, S. Bang, T.-H. Kim, K. Hong, S. Kim, S. Kim, B.-G. Park, and W. Y. Choi, "Electric-Field-Induced Metal Filament Formation in Cobalt-Based CBRAM Observed by TEM," ACS Applied Electronic Materials, vol. 5, no. 3, pp. 1834-1843, 2023.
[19] W. Banerjee, X. Xu, H. Lv, Q. Liu, S. Long, and M. Liu, "Complementary Switching in 3D Resistive Memory Array," Advanced Electronic Materials, vol. 3, no. 12, 2017.
[20] Y. Zhang, G.-Q. Mao, X. Zhao, Y. Li, M. Zhang, Z. Wu, W. Wu, H. Sun, Y. Guo, L. Wang, X. Zhang, Q. Liu, H. Lv, K.-H. Xue, G. Xu, X. Miao, S. Long, and M. Liu, "Evolution of the conductive filament system in HfO2-based memristors observed by direct atomic-scale imaging," Nature Communications, vol. 12, no. 1, p. 7232, 2021.
[21] U. Celano, Y. Yin Chen, D. J. Wouters, G. Groeseneken, M. Jurczak, and W. Vandervorst, "Filament observation in metal-oxide resistive switching devices," Applied Physics Letters, vol. 102, no. 12, 2013.
[22] Y. Yang, P. Gao, S. Gaba, T. Chang, X. Pan, and W. Lu, "Observation of conducting filament growth in nanoscale resistive memories," Nat Commun, vol. 3, p. 732, 2012.
[23] G. Bersuker, D. C. Gilmer, D. Veksler, P. Kirsch, L. Vandelli, A. Padovani, L. Larcher, K. McKenna, A. Shluger, V. Iglesias, M. Porti, and M. Nafría, "Metal oxide resistive memory switching mechanism based on conductive filament properties," Journal of Applied Physics, vol. 110, no. 12, 2011.
[24] P. Y. Chen and S. Yu, "Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design," IEEE Transactions on Electron Devices, vol. 62, no. 12, pp. 4022-4028, 2015.
[25] S. Yu, X. Guan, and H. S. P. Wong, "On the Switching Parameter Variation of Metal Oxide RRAM—Part II: Model Corroboration and Device Design Strategy," IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 1183-1188, 2012.
[26] A. Padovani, L. Larcher, O. Pirrotta, L. Vandelli, and G. Bersuker, "Microscopic Modeling of HfOx RRAM Operations: From Forming to Switching," IEEE Transactions on Electron Devices, vol. 62, no. 6, pp. 1998-2006, 2015.
[27] J. Reuben, M. Biglari, and D. Fey, "Incorporating Variability of Resistive RAM in Circuit Simulations Using the Stanford–PKU Model," IEEE Transactions on Nanotechnology, vol. 19, pp. 508-518, 2020.
[28] C. F. Yang, C. Y. Wu, M. C. Shih, M. T. Yang, M. H. Yang, Y. T. Wu, T. C. Chien, C. W. Lai, S. C. Tsai, W. T. Chu, and A. Hung, "Demonstration of High Endurance Capability on Mega-Bit RRAM Macro and Model of ppm Level Failures," in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, pp. 318-319.
[29] A. S. Foster, A. L. Shluger, and R. M. Nieminen, "Mechanism of Interstitial Oxygen Diffusion in Hafnia," Physical Review Letters, vol. 89, no. 22, p. 225901, 2002.
[30] U. B. Han and J. S. Lee, "Bottom-up synthesis of ordered metal/oxide/metal nanodots on substrates for nanoscale resistive switching memory," Sci Rep, vol. 6, p. 25537, 2016.
[31] Y. Yang, M. Xu, S. Jia, B. Wang, L. Xu, X. Wang, H. Liu, Y. Liu, Y. Guo, L. Wang, S. Duan, K. Liu, M. Zhu, J. Pei, W. Duan, D. Liu, and H. Li, "A new opportunity for the emerging tellurium semiconductor: making resistive switching devices," Nat Commun, vol. 12, no. 1, p. 6081, 2021.
[32] E. Esmanhotto, L. Brunet, N. Castellani, D. Bonnet, T. Dalgaty, L. Grenouillet, D. R. B. Ly, C. Cagli, C. Vizioz, N. Allouti, F. Laulagnet, O. Gully, N. Bernard-Henriques, M. Bocquet, G. Molas, P. Vivet, D. Querlioz, J. Portal, S. Mitra, F. Andrieu, C. Fenouillet-Beranger, E. Nowak, and E. Vianello, "High-Density 3D Monolithically Integrated Multiple 1T1R Multi-Level-Cell for Neural Networks," in 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 36.5.1-36.5.4.
[33] T. W. Hickmott, "Low-Frequency Negative Resistance in Thin Anodic Oxide Films," Journal of Applied Physics, vol. 33, pp. 2669-2682, 1962.
[34] I. G. Baek, M. S. Lee, S. Seo, M. J. Lee, D. H. Seo, D. S. Suh, J. C. Park, S. O. Park, H. S. Kim, I. K. Yoo, U. I. Chung, and J. T. Moon, "Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses," in IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., 2004, pp. 587-590.
[35] S. Yu, P. Y. Chen, Y. Cao, L. Xia, Y. Wang, and H. Wu, "Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect," in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 17.3.1-17.3.4.
[36] Y. Ding, J. Yang, Y. Liu, J. Gao, Y. Wang, P. Jiang, S. Lv, Y. Chen, B. Wang, W. Wei, T. Gong, K. H. Xue, Q. Luo, X. Miao, and M. Liu, "16-layer 3D Vertical RRAM with Low Read Latency (18ns), High Nonlinearity (>5000) and Ultra-low Leakage Current (~pA) Self-Selective Cells," in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, pp. 1-2.
[37] Y. H. Huang, Y. C. Hsieh, Y. C. Lin, Y. D. Chih, E. Wang, J. Chang, Y. C. King, and C. J. Lin, "High Density Embedded 3D Stackable Via RRAM in Advanced MCU Applications," in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, pp. 1-2.
[38] Y. S. Kim, M. W. Son, and K. M. Kim, "Memristive Stateful Logic for Edge Boolean Computers," Advanced Intelligent Systems, vol. 3, no. 7, p. 2000278, 2021.
[39] W. Song, M. Rao, Y. Li, C. Li, Y. Zhuo, F. Cai, M. Wu, W. Yin, Z. Li, Q. Wei, S. Lee, H. Zhu, L. Gong, M. Barnell, Q. Wu, P. A. Beerel, M. S.-W. Chen, N. Ge, M. Hu, Q. Xia, and J. J. Yang, "Programming memristor arrays with arbitrarily high precision for analog computing," Science, vol. 383, no. 6685, pp. 903-910, 2024.
[40] W. Haensch, A. Raghunathan, K. Roy, B. Chakrabarti, C. M. Phatak, C. Wang, and S. Guha, "Compute in-Memory with Non-Volatile Elements for Neural Networks: A Review from a Co-Design Perspective," Adv Mater, vol. 35, no. 37, p. e2204944, 2023.
[41] W. Wan, R. Kubendran, C. Schaefer, S. B. Eryilmaz, W. Zhang, D. Wu, S. Deiss, P. Raina, H. Qian, B. Gao, S. Joshi, H. Wu, H. P. Wong, and G. Cauwenberghs, "A compute-in-memory chip based on resistive random-access memory," Nature, vol. 608, no. 7923, pp. 504-512, 2022.
[42] S. D. Spetalnick, M. Chang, S. Konno, B. Crafton, A. S. Lele, W. S. Khwa, Y. D. Chih, M. F. Chang, and A. Raychowdhury, "A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation," in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, pp. 1-2.
[43] A. Reuther, P. Michaleas, M. Jones, V. Gadepally, S. Samsi, and J. Kepner, "AI Accelerator Survey and Trends," in 2021 IEEE High Performance Extreme Computing Conference (HPEC), 2021, pp. 1-9.
[44] J. Choquette, W. Gandhi, O. Giroux, N. Stam, and R. Krashinsky, "NVIDIA A100 Tensor Core GPU: Performance and Innovation," IEEE Micro, vol. 41, no. 2, pp. 29-35, 2021.
[45] F. Akopyan, J. Sawada, A. Cassidy, R. Alvarez-Icaza, J. Arthur, P. Merolla, N. Imam, Y. Nakamura, P. Datta, G. J. Nam, B. Taba, M. Beakes, B. Brezzo, J. B. Kuang, R. Manohar, W. P. Risk, B. Jackson, and D. S. Modha, "TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 10, pp. 1537-1557, 2015.
[46] C. C. Chou, Z. J. Lin, P. L. Tseng, C. F. Li, C. Y. Chang, W. C. Chen, Y. D. Chih, and T. Y. J. Chang, "An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance," in 2018 IEEE International Solid-State Circuits Conference - (ISSCC), 2018, pp. 478-480.
[47] Y. C. Chen, C. C. Lin, S. T. Hu, C. Y. Lin, B. Fowler, and J. Lee, "A Novel Resistive Switching Identification Method through Relaxation Characteristics for Sneak-path-constrained Selectorless RRAM application," Sci Rep, vol. 9, no. 1, p. 12420, 2019.
[48] J. Woo, X. Peng, and S. Yu, "Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing," in 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, pp. 1-4.
[49] M. Y. Chee, P. A. Dananjaya, G. J. Lim, Y. Du, and W. S. Lew, "Frequency-Dependent Synapse Weight Tuning in 1S1R with a Short-Term Plasticity TiOx-Based Exponential Selector," ACS Applied Materials & Interfaces, vol. 14, no. 31, pp. 35959-35968, 2022.
[50] J. Woo, D. Lee, G. Choi, E. Cha, S. Kim, W. Lee, S. Park, and H. Hwang, "Selector-less RRAM with non-linearity of device for cross-point array applications," Microelectronic Engineering, vol. 109, pp. 360-363, 2013.
[51] J. Joshua Yang, M.-X. Zhang, M. D. Pickett, F. Miao, J. Paul Strachan, W.-D. Li, W. Yi, D. A. A. Ohlberg, B. Joon Choi, W. Wu, J. H. Nickel, G. Medeiros-Ribeiro, and R. Stanley Williams, "Engineering nonlinearity into memristors for passive crossbar applications," Applied Physics Letters, vol. 100, no. 11, 2012.
[52] C. L. Lo, T. H. Hou, M. C. Chen, and J. J. Huang, "Dependence of Read Margin on Pull-Up Schemes in High-Density One Selector–One Resistor Crossbar Array," IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 420-426, 2013.
[53] J. H. Yoon, M. Chang, W. S. Khwa, Y. D. Chih, M. F. Chang, and A. Raychowdhury, "A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection," IEEE Journal of Solid-State Circuits, vol. 57, no. 1, pp. 68-79, 2022.
[54] S. Kim, J. Zhou, and W. D. Lu, "Crossbar RRAM Arrays: Selector Device Requirements During Write Operation," IEEE Transactions on Electron Devices, vol. 61, no. 8, pp. 2820-2826, 2014.
[55] T. D. Dongale, G. U. Kamble, D. Y. Kang, S. S. Kundale, H.-M. An, and T. G. Kim, "Recent Progress in Selector and Self‐Rectifying Devices for Resistive Random‐Access Memory Application," physica status solidi (RRL) – Rapid Research Letters, vol. 15, no. 9, 2021.
[56] Z. Wang, J. Kang, G. Bai, G. Zhong, B. Wang, Y. Ling, Q. Chen, L. Bao, L. Wu, Y. Cai, J. Robertson, and R. Huang, "Self-Selective Resistive Device With Hybrid Switching Mode for Passive Crossbar Memory Application," IEEE Electron Device Letters, vol. 41, no. 7, pp. 1009-1012, 2020.
[57] J. J. Yang, J. Borghetti, D. Murphy, D. R. Stewart, and R. S. Williams, "A Family of Electronically Reconfigurable Nanodevices," Advanced Materials, vol. 21, no. 37, pp. 3754-3758, 2009.
[58] M. D. Pickett, J. Borghetti, J. J. Yang, G. Medeiros‐Ribeiro, and R. S. Williams, "Coexistence of Memristance and Negative Differential Resistance in a Nanoscale Metal‐Oxide‐Metal System," Advanced Materials, vol. 23, no. 15, pp. 1730-1733, 2011.
[59] Q. Luo, X. Xu, H. Liu, H. Lv, T. Gong, S. Long, Q. Liu, H. Sun, W. Banerjee, L. Li, J. Gao, N. Lu, S. S. Chung, J. Li, and M. Liu, "Demonstration of 3D vertical RRAM with ultra low-leakage, high-selectivity and self-compliance memory cells," in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 10.2.1-10.2.4.
[60] U. Chand, K. C. Huang, C. Y. Huang, and T. Y. Tseng, "Mechanism of Nonlinear Switching in HfO2-Based Crossbar RRAM With Inserting Large Bandgap Tunneling Barrier Layer," IEEE Transactions on Electron Devices, vol. 62, no. 11, pp. 3665-3670, 2015.
[61] Z. Wang, J. Kang, Z. Yu, Y. Fang, Y. Ling, Y. Cai, R. Huang, and Y. Wang, "Modulation of nonlinear resistive switching behavior of a TaOx-based resistive device through interface engineering," Nanotechnology, vol. 28, no. 5, p. 055204, 2017.
[62] Z. Wang, Q. Zheng, J. Kang, Z. Yu, G. Zhong, Y. Ling, L. Bao, S. Bao, G. Bai, S. Zheng, Y. Cai, J. Robertson, and R. Huang, "Self-Activation Neural Network Based on Self-Selective Memory Device With Rectified Multilevel States," IEEE Transactions on Electron Devices, vol. 67, no. 10, pp. 4166-4171, 2020.
[63] Y. C. Chen, J. Lee, and C. Y. Lin, "Dual-Functional Hybrid Selectorless RRAM and Selection Device for Memory Array Application," IEEE Transactions on Electron Devices, vol. 68, no. 9, pp. 4363-4367, 2021.
[64] P. H. Chen, C. Y. Lin, T. C. Chang, J. K. Eshraghian, Y. T. Chao, W. D. Lu, and S. M. Sze, "Investigating Selectorless Property within Niobium Devices for Storage Applications," ACS Appl Mater Interfaces, vol. 14, no. 1, pp. 2343-2350, 2022.
[65] A. Prakash, J. Park, J. Song, J. Woo, E. J. Cha, and H. Hwang, "Demonstration of Low Power 3-bit Multilevel Cell Characteristics in a TaOx-Based RRAM by Stack Engineering," IEEE Electron Device Letters, vol. 36, no. 1, pp. 32-34, 2015.
[66] C. Mahata, C. Lee, Y. An, M.-H. Kim, S. Bang, C. S. Kim, J.-H. Ryu, S. Kim, H. Kim, and B.-G. Park, "Resistive switching and synaptic behaviors of an HfO2/Al2O3 stack on ITO for neuromorphic systems," Journal of Alloys and Compounds, vol. 826, 2020.
[67] J. Woo, K. Moon, J. Song, S. Lee, M. Kwak, J. Park, and H. Hwang, "Improved Synaptic Behavior Under Identical Pulses Using AlOx/HfO2 Bilayer RRAM Array for Neuromorphic Systems," IEEE Electron Device Letters, vol. 37, no. 8, pp. 994-997, 2016.
[68] F. Alibart, L. Gao, B. D. Hoskins, and D. B. Strukov, "High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm," Nanotechnology, vol. 23, no. 7, p. 075201, 2012.
[69] D. Panda, C. A. Chu, A. Pradhan, S. Chandrasekharan, B. Pattanayak, S. M. Sze, and T. Y. Tseng, "Synaptic behaviour of TiOx/HfO2 RRAM enhanced by inserting ultrathin Al2O3 layer for neuromorphic computing," Semiconductor Science and Technology, vol. 36, no. 4, 2021.
[70] F. Cüppers, S. Menzel, C. Bengel, A. Hardtdegen, M. von Witzleben, U. Böttger, R. Waser, and S. Hoffmann-Eifert, "Exploiting the switching dynamics of HfO2-based ReRAM devices for reliable analog memristive behavior," APL Materials, vol. 7, no. 9, 2019.
[71] E. Esmanhotto, T. Hirtzlin, D. Bonnet, N. Castellani, J.-M. Portal, D. Querlioz, and E. Vianello, "Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy," Advanced Intelligent Systems, vol. 4, no. 11, p. 2200145, 2022.
[72] W. Shim, J.-s. Seo, and S. Yu, "Two-step write–verify scheme and impact of the read noise in multilevel RRAM-based inference engine," Semiconductor Science and Technology, vol. 35, no. 11, p. 115026, 2020.
[73] S. Wang, L. Song, W. Chen, G. Wang, E. Hao, C. Li, Y. Hu, Y. Pan, A. Nathan, G. Hu, and S. Gao, "Memristor‐Based Intelligent Human‐Like Neural Computing," Advanced Electronic Materials, vol. 9, no. 1, 2022.
[74] N. Masaoka, Y. Hayashi, T. Tohei, and A. Sakai, "Interface engineering of amorphous gallium oxide crossbar array memristors for neuromorphic computing," Japanese Journal of Applied Physics, vol. 62, no. SC, p. SC1035, 2023.
[75] C. Li, D. Belkin, Y. Li, P. Yan, M. Hu, N. Ge, H. Jiang, E. Montgomery, P. Lin, Z. Wang, W. Song, J. P. Strachan, M. Barnell, Q. Wu, R. S. Williams, J. J. Yang, and Q. Xia, "Efficient and self-adaptive in-situ learning in multilayer memristor neural networks," Nat Commun, vol. 9, no. 1, p. 2385, 2018.
[76] M. Arita, A. Takahashi, Y. Ohno, A. Nakane, A. Tsurumaki-Fukuchi, and Y. Takahashi, "Switching operation and degradation of resistive random access memory composed of tungsten oxide and copper investigated using in-situ TEM," Sci Rep, vol. 5, p. 17103, 2015.
[77] X. Zhao, S. Liu, J. Niu, L. Liao, Q. Liu, X. Xiao, H. Lv, S. Long, W. Banerjee, W. Li, S. Si, and M. Liu, "Confining Cation Injection to Enhance CBRAM Performance by Nanopore Graphene Layer," Small, vol. 13, no. 35, 2017.
[78] K.-J. Gan, W.-C. Chang, P.-T. Liu, and S. M. Sze, "Investigation of resistive switching in copper/InGaZnO/Al2O3-based memristor," Applied Physics Letters, vol. 115, no. 14, 2019.
[79] K. Nagao, J. B. Neaton, and N. W. Ashcroft, "First-principles study of adhesion atCu/SiO2interfaces," Physical Review B, vol. 68, no. 12, 2003.
[80] S. W. Russell, S. A. Rafalski, R. L. Spreitzer, J. Li, M. Moinpour, F. Moghadam, and T. L. Alford, "Enhanced adhesion of copper to dielectrics via titanium and chromium additions and sacrificial reactions," Thin Solid Films, vol. 262, no. 1, pp. 154-167, 1995.
[81] E. Linn, R. Rosezin, S. Tappertzhofen, U. Böttger, and R. Waser, "Beyond von Neumann—logic operations in passive crossbar arrays alongside memory operations," Nanotechnology, vol. 23, no. 30, p. 305205, 2012.
[82] K.-E. Harabi, T. Hirtzlin, C. Turck, E. Vianello, R. Laurent, J. Droulez, P. Bessière, J.-M. Portal, M. Bocquet, and D. Querlioz, "A memristor-based Bayesian machine," Nature Electronics, 2022.
[83] W. Wang, S. Liu, Q. Li, T. Shi, F. Zhang, H. Liu, N. Li, Y. Wang, Y. Sun, B. Song, H. Xu, and Q. Liu, "Fast and Reconfigurable Logic Synthesis in Memristor Crossbar Array," Advanced Intelligent Systems, vol. 4, no. 12, 2022.
[84] J. Backus, "Can programming be liberated from the von Neumann style? a functional style and its algebra of programs," Commun. ACM, vol. 21, no. 8, pp. 613–641, 1978.
[85] H. Jun, J. Cho, K. Lee, H. Y. Son, K. Kim, H. Jin, and K. Kim, "HBM (High Bandwidth Memory) DRAM Technology and Architecture," in 2017 IEEE International Memory Workshop (IMW), 2017, pp. 1-4.
[86] M. J. Park, J. Lee, K. Cho, J. Park, J. Moon, S. H. Lee, T. K. Kim, S. Oh, S. Choi, Y. Choi, H. S. Cho, T. Yun, Y. J. Koo, J. S. Lee, B. K. Yoon, Y. J. Park, S. Oh, C. K. Lee, S. H. Lee, H. W. Kim, Y. Ju, S. K. Lim, K. Y. Lee, S. H. Lee, W. S. We, S. Kim, S. M. Yang, K. Lee, I. K. Kim, Y. Jeon, J. H. Park, J. C. Yun, S. Kim, D. Y. Lee, S. H. Oh, J. H. Shin, Y. Lee, J. Jang, and J. Cho, "A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization," IEEE Journal of Solid-State Circuits, vol. 58, no. 1, pp. 256-269, 2023.
[87] S. Xie, C. Ni, A. Sayal, P. Jain, F. Hamzaoglu, and J. P. Kulkarni, "16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing," in 2021 IEEE International Solid-State Circuits Conference (ISSCC), 2021, vol. 64, pp. 248-250.
[88] W. S. Khwa, J. J. Chen, J. F. Li, X. Si, E. Y. Yang, X. Sun, R. Liu, P. Y. Chen, Q. Li, S. Yu, and M. F. Chang, "A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors," in 2018 IEEE International Solid-State Circuits Conference - (ISSCC), 2018, pp. 496-498.
[89] X. Si, J. J. Chen, Y. N. Tu, W. H. Huang, J. H. Wang, Y. C. Chiu, W. C. Wei, S. Y. Wu, X. Sun, R. Liu, S. Yu, R. S. Liu, C. C. Hsieh, K. T. Tang, Q. Li, and M. F. Chang, "24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning," in 2019 IEEE International Solid-State Circuits Conference - (ISSCC), 2019, pp. 396-398.
[90] K. KIERS, T. KLEIN, J. KOLB, S. PRICE, and J. C. SPROTT, "CHAOS IN A NONLINEAR ANALOG COMPUTER," International Journal of Bifurcation and Chaos, vol. 14, no. 08, pp. 2867-2873, 2004.
[91] M. A. Zidan, Y. Jeong, J. Lee, B. Chen, S. Huang, M. J. Kushner, and W. D. Lu, "A general memristor-based partial differential equation solver," Nature Electronics, vol. 1, no. 7, pp. 411-420, 2018.
[92] K. Roy, A. Jaiswal, and P. Panda, "Towards spike-based machine intelligence with neuromorphic computing," Nature, vol. 575, no. 7784, pp. 607-617, 2019.
[93] T. Gokmen and W. Haensch, "Algorithm for Training Neural Networks on Resistive Device Arrays," Front Neurosci, vol. 14, p. 103, 2020.
[94] R. Yuan, P. J. Tiw, L. Cai, Z. Yang, C. Liu, T. Zhang, C. Ge, R. Huang, and Y. Yang, "A neuromorphic physiological signal processing system based on VO2 memristor for next-generation human-machine interface," Nature Communications, vol. 14, no. 1, 2023.
[95] E. Linn, R. Rosezin, C. Kugeler, and R. Waser, "Complementary resistive switches for passive nanocrossbar memories," Nat Mater, vol. 9, no. 5, pp. 403-6, 2010.
[96] J. Borghetti, G. S. Snider, P. J. Kuekes, J. J. Yang, D. R. Stewart, and R. S. Williams, "'Memristive' switches enable 'stateful' logic operations via material implication," Nature, vol. 464, no. 7290, pp. 873-6, 2010.
[97] G. Liu, S. Shen, P. Jin, G. Wang, and Y. Liang, "Design of Memristor-Based Combinational Logic Circuits," Circuits, Systems, and Signal Processing, vol. 40, no. 12, pp. 5825-5846, 2021.
[98] S. Seo, M. J. Lee, D. H. Seo, E. J. Jeoung, D. S. Suh, Y. S. Joung, I. K. Yoo, I. R. Hwang, S. H. Kim, I. S. Byun, J. S. Kim, J. S. Choi, and B. H. Park, "Reproducible resistance switching in polycrystalline NiO films," Applied Physics Letters, vol. 85, no. 23, pp. 5655-5657, 2004.
[99] Y. Bai, H. Wu, K. Wang, R. Wu, L. Song, T. Li, J. Wang, Z. Yu, and H. Qian, "Stacked 3D RRAM Array with Graphene/CNT as Edge Electrodes," Scientific Reports, vol. 5, no. 1, p. 13785, 2015.
[100] E. R. Hsieh, X. Zheng, B. Q. Le, Y. C. Shih, R. M. Radway, M. Nelson, S. Mitra, and S. Wong, "Four-Bits-Per-Memory One-Transistor-and-Eight-Resistive-Random-Access-Memory (1T8R) Array," IEEE Electron Device Letters, vol. 42, no. 3, pp. 335-338, 2021.
[101] R. An, Y. Li, J. Tang, B. Gao, Y. Du, J. Yao, Y. Li, W. Sun, H. Zhao, J. Li, Q. Qin, Q. Zhang, S. Qiu, Q. Li, Z. Li, H. Qian, and H. Wu, "A Hybrid Computing-In-Memory Architecture by Monolithic 3D Integration of BEOL CNT/IGZO-based CFET Logic and Analog RRAM," in 2022 International Electron Devices Meeting (IEDM), 2022, pp. 18.1.1-18.1.4.