金氧半導體場效電晶體(MOSFET)是過去三十年來，微電子工業最重要的技術。根據國際半導體技術所設定的指標(ITRS Roadmap)，半導體產業的技術發展與電晶體的特徵尺寸隨著莫爾定律的預測，在相同面積的晶圓下生產同樣規格的IC，每隔18個月，IC的積體密度就可增加一倍；換算為成本，即每隔18個月成本可降低五成，平均每年成本可降低三成多。換言之，元件尺寸逐漸微縮小、元件密度增加、效能提升，電容會減小，從而提高運行速度。目前量產的多鰭場效電晶體(Multi-FinFET)，因其多鰭以並聯的方式排列後，電晶體元件的等效通道寬度，和微縮元件通道長度，使得電流加大，而提升多鰭場效電晶體元件的控制能力，對元件的電性能更有效控制。但多鰭結構在單一通道下，會因其整體總電流量的多寡、彼此的耦合效應、不均的等效鰭高、鰭數的多寡、SiGe和CESL(Contact Etch Stop Layer)SiN對通道造成擠壓應力( Compressive strain)，而影響電晶體的臨界電壓、次臨界擺幅、電導與汲極電流大小，即控制閘極通道臨界電壓的因素在多鰭結構中是相互影響。相對地，也可以利用TiN厚度調變功函數和參雜濃度的不同來改變臨界電壓；功函數越大，其載子能階越偏向價帶，對費米能（Fermi energy）的能帶差也越小，故電子要越過的阻礙也就越小，即臨界電壓也越小；換言之，金屬閘極之不同的TiN厚度，越厚的TiN，越能阻擋Al原子從TiAl層中擴散至而累積在TiN與HfO2介面，產生Al-O dipole而使EWF偏移至中能隙，造成pFinFET之能帶差變大，臨界電壓變也大。所以利用調變TiN厚度，以獲得合適的臨界電壓，再配合線路設計，達到元件設計要求，是元件設計重要的調變方法。
本論文將以熱載子注入(Hot Carrier Injection，HCI)壓迫方法，對鰭式場效電晶體之不同鰭數目結構，不同通道長度和不同TiN厚度，進行元件可靠度壓迫偏壓測試。當元件通道長度縮短，於汲極靠近通道的地方電場高，以致電子能量高，產生衝擊游離(Impact Ionization)進而撞擊出電子電洞對(E-H Pairs)，並形成介面層缺陷，載子會被缺陷所捕捉，造成臨界電壓下降及閘極電壓對元件通道失控，無法關掉電流，使得元件效能降低並產生嚴重的退化。因此通道長度縮短，將衍生出短通道效應：包括Vth下降、汲極引發位能障下降、次臨界斜率上升。還有因為部份載子被源極及汲極的空乏區共享，造成臨界電壓下降(Vth Roll-off)，導致次臨界電流Subthreshold Current)上升，MOSFET閘極電壓(VG)的臨界電壓(Vth)下降，使得對汲極電流(Id)的控制能力下降。故短通道元件的退化比長通道嚴重。然而SiGe和CESL SiN對通道造成擠壓應力( Compressive strain)，而影響臨界電壓、次臨界擺幅、電導與汲極電流大小，其表示對閘極通道的控制能力在多重鰭結構中是相互影響。且SiGe和CESL SiN擠壓應力使得其影響大於耦合電場效應，導致等效通道變短；且鰭根鰭間的電荷斥力造成耦合電場效應導致通道內部局部垂直電場下降，反轉電荷的密度降低，閘極對通道的控制能力變差和因元件製程因數，其等效鰭高改變，反轉電荷的密度改變，造成歸一化後，汲極電流隨著鰭數改變，而改變，閘極對通道的控制能力也被改變。故多重鰭元件整體增加了等效通道寬度，故能提供較佳的元件電性特性；而多重鰭的耦合效應、SiGe和CESL SiN對通道造成擠壓應力，等效鰭高因數，和鰭數的多寡，而影響臨界電壓、次臨界擺幅、電導與汲極電流大小，其表示對閘極通道的電性特性控制能力在多重鰭結構中是相互影響；且多重鰭元件退化比單鰭元件嚴重。另一方面，TiN功函數厚度調變後的LVt Base有效壓迫電壓(Veff)作用在Oxide的作用力比SVt Base大，且短通道結構下，此閘極和汲極的等效偏壓電場會對元件造成最嚴峻的熱載子破壞，導致LVt Base和短通道結構有嚴重的退化。故就元件整體的退化趨勢而言，SVt Base長通道元件比LVt Base短通道結構，擁有較佳元件穩定性及可靠度。

At present, Multi-FinFET has produced devices with gate length miniaturization to increase drain current、average electron energy、mobility、GM and enhancing the effective device control, but reliability degradation due to the short channel effect. The multi-fin structure tends to affect the threshold voltage, subthreshold swing, transconduction, drain current and gate channel control ability due to coupling effect, equivalent fin height, manufacturing process, and compressive strain of SiGe, CESL (Contact Etch Stop Layer) SiN on the channel. To mitigate these adverse effects, the threshold voltage is changed by modulating the TiN thickness to vary its associated work function, and both the band gap and barrier are lower with a thicker TiN thickness of the LVt Base which closes the carrier energy to the valency band. Thus, the diffusion of Al atoms from the TiAl layer to bottom barrier metal and accumulated in the interface of TiN and HfO2 can be prevented, and LVt Base has a larger effective stress voltage (Veff.) and severe hot-carrier than the SVt Base on the oxide layer of a thicker TiN thickness to damage to the device and results in serious degradation of the LVt Base structure. Therefore, the SVt Base structure offers better stability, reliability, and lower stress voltage than the LVt base structure due to a thinner TiN thickness.

[1] F Schwierz, J Pezoldt, R Granzner, “Two-dimensional materials and their prospects in transistor electronics”, Nanoscale, vol.7, pp. 8261-8283,2015
[2] Charu Gupta, Anshul Gupta, Reinaldo A. Vega, Terence B. Hook, Abhisek Dixit, “Impact of hot-carrier degradation on drain-induced barrier lowering in multifin SOI n-channel FinFETs with self-heating”, IEEE Transactions on Electron Device, vol.67, issue 5,2208-2212,2020
[3] Hsin-Wen Su, Yiming Li, Yu-Yu Chen, Chieh-Yang Chen, Han-Tung Chang, “Drain-induced-barrier lowering and subthreshold swing fluctuations in 16-nm-gate bulk FinFET devices induced by random discrete dopants”,70th Device Research Conference, pp.109-110,2012
[4] Y Li, C H Hwang, “Discrete-dopant-fluctuated threshold voltage roll-off in sub-16 nm bulk fin-type field effect transistors”, Japanese Journal of Applied Physics, vol. 47, pp.2580-2584,2008
[5] Hakkee Jung, “Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET”, International Journal of Electrical and Computer Engineering (IJECE), vol.9 issue 1, pp.163-169,2019
[6] Pedro C Feijoo, Thomas Kauerauf, María Toledano-Luque, Mitsuhiro Togo, Enrique SanAndrés, Guido Groeseneken,” Time-dependent dielectric breakdown on subnanometer EOT nMOS FinFETs”, IEEE Transactions on Device and Materials Reliability, vol.12, pp.166-170,2012
[7] Kexin Yang, Taizhi Liu, Rui Zhang, Linda Milor,” A comprehensive time-dependent dielectric breakdown lifetime simulator for both traditional CMOS and FinFET technology”, IEEETnsactions on VLSI Systems, vol. 26, pp. 2470-2482,2018
[8] Miao Xu, Huilong Zhu, Lichuan Zhao, Huaxiang Yin, Jian Zhong, Junfeng Li, Chao Zhao, Dapeng Chen, TianchunYe,” Improved short channel effect control in bulk FinFETs with vertical implantation to form self-aligned halo and punch-through stop pocket”, IEEE Electron Device Letters, vol.36, issue 7, pp.648-650,2015
[9] G. Molas Marc Bocquet J. Buckley H. Grampeix M. Gély J.P. Colonna F. Martin P. Brianceau V. Vidal C. Bongiorno S. Lombardo G. Pananakakis 1 G. Ghibaudo 1 B. de Salvo S. Deleonibus, “Evaluation of HfAlO high-k materials for control dielectric applications in non-volatile memories”, ELSEVIER Microelectronic Engineering, vol.85, issue 12, pp.2393-2399,2008
[10] Xiongfei Yu, Chunxiang Zhu, “Mobility enhancement in TaN metal-gate MOSFETs using tantalum incorporated HfO2 gate dielectric”, IEEE Electron Device Letters, vol.25, issue 7, pp.501-503,2004
[11] Miao Xu, Huilong Zhu, Lichuan Zhao, Huaxiang Yin, Jian Zhong, Junfeng Li, Chao Zhao, Dapeng Chen, Ianchun Ye, “Ivestigation on the lateral trapistributions in nanoscale MOSFETs during hot carrier stress”, IEEE Electron Device Letters, vol. 40, issue 4, pp. 490-493,2015
[12] Masaru Kadoshima, Takeo Matsuki, Seiichi Miyazaki, Kenji Shiraishi, ToyohiroChikyo, Keisaku Yamada, Takayuki Aoyama, Yasuo Nara, Yuzuru Ohji,” Effective-work-function control by varying the TiN thickness in poly-Si/TiN gate electrodes for scaled High-k CMOSFETs”, IEEE Electron Device Letters, vol.30, issue 5, pp.466-468,2009
[13] Y Li, H M Chou, JW Lee, “Investigation of Electrical Characteristics on Surrounding-Gate and Omega-Shaped-Gate Nanowire FinFETs”, IEEE Transactions on Nanotechnology, vol. 4, issue 5, pp. 510-516,2005
[14] S Ramey, A Ashutosh, C Auth, J Clifford, M Hattendorf, J Hicks, R James, A Rahman, V Sharma, A St Amour, C Wiegand, “Intrinsic transistor reliability improvements from 22nm tri-gate technology”, IEEE International Reliability Physics Symposium, pp. 4C.5.1-4C.5.5,2013
[15] Brad D, Gaynor, Soha Hassoun,” Fin shape impact on FinFET leakage with application to multithreshold and ultra low leakage FinFET design”, IEEE Trans. Electron Devices Electron Devices, vol. 61, issue 8, pp. 2738-2744,2014
[16] Leland Chang, Yang Kyu Choi, Jakub Kedzierski, Nick Lindert, Peiqi Xuan, Jeffrey Bokor, Chen-Ming Hu, Tsu Jae King, “Moore's law lives on [CMOS transistors]”, IEEE Circuits and Devices Magazine, vol.19, issue 1, pp. 35-42,2003
[17] Seiji Horiguchi, Toshio Kobayashi, and Kazuyuki Saito, “Interface-trap generation modeling of Fowler–Nordheim tunnel injection into ultrathin gate oxide”, Journal of Applied Physics, vol. 58, pp. 387-391,1985
[18] J Cai, “Theory and experiments of electron-hole recombination at silicon/silicon dioxide interface traps and tunneling in thin oxide MOS transistors”, University of Florida, vol.61-08, Section B, pp.4301,2000
[19] Yoshinari Kamakura, Kazuaki Deguchi, Akihiro Ishida, Shigeyasu Uno, Kenji Taniguchi, “Degradation of direct-tunneling gate oxide under hot hole injection”, Osaka University, Japan, vol.140, issue 4, pp. 54-61,2002
[20] G Saini, A K Rana, “Physical scaling limits of FinFET Structure: A Simulation Study”, International Journal of VLSI Design & Communication Systems, vol. 2, pp. 26-35,2011
[21] Ma Xueli, Yang Hong, Wang Wenwu, Yin Huaxiang, Zhu Huilong, Zhao Chao, Chen Dapeng, Ye Tianchun, “The effects of process condition of top-TiN and TaN thickness on the effective work function of MOSCAP with high-kmetal gate stacks”, Chinese Institute of Electronics, vol.35, issue 10, article id. 106002,2014
[22] J Welser, J L Hoyt, S Takagi, J F Gibbons, “Strain dependence of the performance enhancement in strained-Si n-MOSFETs”, International Electron Devices Meeting, San Francisco, CA, USA, pp. 373-376,1994
[23] K Rim, J Welser, J L Hoyt, J F Gibbons, “Enhanced hole mobilities in surface-channel strained-Si pMOSFETs”, International Electron Devices Meeting, Washington, DC, USA, pp. 517-520,1995
[24] S.E. Thompson, M Armstrong, C Auth, M Alavi, M Buehler, R Chau, S Cea, T Ghani, G Glass, T Hoffman, "A 90-nm logictechnology featuring strained-silicon", IEEE Transactions on Electron Devices, vol.51, issue11, pp. 1790-1797,2004
[25] C H Ge, C C Lin, C H Ko, C C Huang, Y C Huang, B W Chan, B C Perng, C C Sheu, P Y Tsai, L G Yao, "Process-strained Si (PSS) CMOS technology featuring 3D strain engineering", Electron Devices Meeting, IEDM'03 Technical Digest. IEEE International, Washington, DC, USA, pp. 73-76,2003
[26]林文欽,“功函數金屬厚度調變對N型多重鰭數鰭式場效電晶體之元件特性和可靠度研究”,國立高雄大學電機工程研究所碩士論文,2019
[27] 陳詩堯, “不同金屬閘極對多重鰭數N型鰭式場效電晶體之可靠度研究”，國立高雄大學電機工程研究所碩士論文,2016
[28]鄭旭廷,“多重鰭數對P型鰭式場效電晶體之電性分析及可靠度研究”，國立高雄大學電機工程研究所碩士論文,2015
[29]T Ytterdal, Y Cheng, T A Fjeldly, “Device modeling for analog and RF CMOS circuit design”, pp. 34-35,2003
[30] B S Doyle, K R Mistry, J Faricelli, “Examination of the time power law dependencies in hot carrier stressing of n-MOS transistors”, IEEE Electron Device Letters, vol. 18, No. 2, pp.51-53,1997
[31] Wen-Kuan Yeh, Wenqi Zhang, Po-Ying Chen, Yi-Lin Yang, “The impact of fin number on device performance and reliability for multi-fin tri-gate n- and p-type FinFET”, IEEE Transactions on Device and Materials Reliability, vol.18, issue 4, pp.555 -560,2018
[32] Francesco Conzatti, Nicola Serra, David Esseni, Marco De Michielis, Alan Paussa, PierpaoloPalestri, Luca Selmi, Stephen M. Thomas, Terence E. Whall, David Leadley, E H C Parker, LiesbethWitters, Martin J Hytch, Etienne Snoeck, T J Wang, W C Lee, Gerben Doornbos, Georgios Vellianitis, Mark J H van Dal, R J P Lander, “Investigation of strain engineering in FinFETs comprising experimental analysis and numerical simulations”, IEEE Transactions on Electron Devices, vol.58, issue 6,pp.1583-1593,2011
[33] E Ungersboeck, V Sverdlov, H Kosina, S. Selberherr, “Strain engineering for CMOS devices”, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, Shanghai, China, pp. 124-127,2006
[34] Jack Kavalieros, Brian Doyle, Suman Datta, Gilbert Dewey, Mark Doczy, Ben Jin, Dan Lionberger, Matthew Metz, Willy Rachmady, Marko Radosavljevic, Uday Shah, Nancy Zelick, Robert Chau,"Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering", Honolulu, HI, USA,2006 Symposium on VLSI Technology, pp.50-51,2006
[35] A F Bello, Abhijeet Paul and Hoon Kim, “Metal gate (TiN, TiC, TaN) film stack stress”, The Minerals, Metals & Materials Society, vol. 44, No. 10, pp. 3236-3242,2015
[36] R Ranjan, K L Pey, C H Tung, “Substrate injection induced ultrafast degradation in HfO2/TaN/TiN gate stack MOSFET”, IEEE International Electron Devices Meeting, San Francisco, CA, USA, pp.1-4,2006
[37] A Veloso, S A Chew, Y Higuchi, L-Å Ragnarsson, E Simoen, “Effective work function engineering for aggressively scaled planar and finfet-based devices with high-k last replacement metal gate technology”, Japanese Journal of Applied Physics, vol. 52, issue 4S, article id. 04CA02,2013
[38] R Singanamalla,"On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO/sub2/ and poly-Si/TiN/HfSiON gate stacks", IEEE Electron Device letters, vol. 27, issue 5, pp.332-334,2006
[39] M Xueli, Y Hong, W Wenwu, Y Huaxiang, “An effective work-function tuning method of nMOSCAP with high-k/metal gate by TiN/TaN double-layer stack thickness”, Chinese Institute of Electronics, vol.35, issue 9, article id. 096001,2014
[40] J Zhang, T Ando, CW Yeung, M Wang, “High-k metal gate fundamental learning and multi-Vt options for stacked nanosheet gate-all-around transistor”, 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 537-540,2017
[41] H Mertens, R Ritzenthaler, A Hikavyy,” Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates”, 2016 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, pp.1-2,2016
[42] Yongwoo Lee, Geon-Hwi Park, Bongsik Choi, JinsuYoon, Hyo-Jin Kim, Dae Hwan Kim, Dong Myong Kim, Min-Ho Kang, Sung-JinChoi, “Design study of the gate-all-around silicon nanosheet MOSFETs”, Semiconductor Science and Technology, vol. 35, issue 3, id.03LT01,2020