在現代晶片設計中，電源消耗已成為一嚴重的問題，最有效降低電源消耗的方式是減少時鐘樹的耗電量。然而，大多數現有的作法是基於正反器為暫存器的時鐘樹架構，節省的電量幅度有其限制。在本篇碩論中，我們利用脈波拴鎖電路取代正反器以更進一步減少動態功率消耗，並且提出脈波拴鎖電路的遷移方法，能夠有效且快速的將正反器架構的時鐘樹遷移為考慮脈波拴鎖電路的時鐘樹。脈波拴鎖電路必須透過脈波產生器產生脈波以使其資料傳遞特性和正反器相似；然而，脈波產生器比一般的緩衝器更為耗電，因此我們必須在使用脈波拴鎖電路節省功率與插入脈波產生器之間選擇取捨。由於有些正反器沒有被替換成脈波拴鎖電路，脈波拴鎖電路和正反器必須同時存在轉移的時鐘樹中。為了考慮時序差問題和負載平衡問題，我們利用最小成本最大網路流的方式來決定時鐘樹的拓樸型態。實驗結果顯示我們所提出的轉移方式可以快速將正反器架構的時鐘樹轉換為脈波拴鎖電路的時鐘樹架構，且更進一步降低時鐘樹的功率消耗。

Minimizing the clock tree has been known as an effective approach to reduce power dissipation in modern circuit designs. However, most existing power-aware clock tree minimization algorithms still focus on optimizing the power in flip-flop-based designs, which may result in limited power savings. In this thesis, we explore the pulsed-latch utilization in a clock tree for further power savings. We are the first study in the literature to propose a novel migration approach to efficiently migrate a flip-flop-based clock tree into a pulsed-latch-based one. In pulsed-latch designs, pulse generators are inserted to drive pulsed latches. However, a pulse generator consumes significantly more power than a pulsed latch. Considering the trade-off between the additional power incurred by pulse generators and the power reduction by the pulsed-latch replacement, we allow the coexistence of flip-flops and pulsed latches, and the design can have a mixture of sinks. To maintain load balance (skew issues) of a clock tree, we determine the clock tree topology by using the minimum-cost maximum-flow network. Experimental results indicate that our migration approach can efficiently migrate a flip-flop-based clock tree to the one with mixture sinks of pulsed latches and flip-flops for further power reduction.

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