隨著積體電路元件尺寸的微縮，導致內層連線的時間延遲比整個元件的時間延遲更加嚴重，更進一步引發內層導線串音和功率消耗過高的問題，因此積體電路元件採用銅導線（低阻值）及低介電常數材料（低電容）來降低時間延遲(RC Delay)效應的問題。現今為了降低多層導線內絕緣體的介電常數，尤以導入多孔性的結構為最有效，但過多的孔隙結構反而使得此種低介電材料成為組織鬆散，機械強度不理想的結構，將不利於積體電路元件整合製程及其封裝工程進行，這些後續的製程外力可輕易跨越介電材料之降伏強度，或本身多孔隙結構過於鬆散，而容易形成電路的導通路徑，致使積體電路元件遭受破壞。因此，本論文將針對兩種不同的低介電常數的材料隨著製程條件的改變時，研究其機械和電氣特性的變化，並成長出符合元件之基本特性要求的機械降伏強度、低介電和低漏電流特性之材料。也基於製程整合問題的考量，本研究並進一步探討低介電薄膜沉積後的製程處理，使其得能應用在奈米銅導線元件上。
本論文第一種低介電材料是利用3MS和氧氣混合氣體再輔以電漿輔助化學氣相沈積法，沈積多孔隙碳氫化矽氧薄膜於矽基材上，以改變腔體氣壓的大小對薄膜結構、介電性質和機械性質之影響進行研究，在其最佳化的製程條件下，並進一步利用O2/CO及NH3電漿後處理的製程，於此種低介電材料表面型成一層保護層，以抵抗外力對低介電材料的破壞。其結果顯示: 在改變壓力之最佳製程條件為2.5 Torr的大氣壓力可得薄膜之楊格係數為19.26 GPa、硬度為3.12 GPa、介電常數為 3.0、漏電流為 6.455×10-9 A/cm2，可將其應用於65奈米及其以上元件之製程。而O2/CO及NH3電漿後處理之製程，將分別於薄膜表面型成SiOx及SiON保護層，以抵抗大氣中或後續製程中水氣的侵襲。
本論文中的第二種低介電材料則是利用DEMS、氧氣以及PROGEN混合氣體輔以電漿輔助化學氣相沈積法，沈積多孔隙碳氫化矽氧薄膜於矽基材上，並以紫外線熱處理移除PROGEN形成多孔性結構並且進行結構改良，以強化低介電材料機械特性，紫外線熱處理為目前多孔隙低介電材料製程所採用，也是積體電路製程較新穎的觀念。此部份研究主要是探討45奈米積體電路元件中後段內層導體(SiOCH)低介電常數薄膜之紫外線熱處理時間和溫度對薄膜特性的影響。低介電常數薄膜(SiOCH)經過不同時間和溫度的紫外線熱處理後，利用傅利葉紅外線光譜分析經紫外線熱處理後薄膜的鍵結型態；經紫外線熱處理後製作成金屬絕緣體半導體結構薄膜，利用HP-428儀器分析其介電性質。
其結果顯示，材料結構方面，薄膜經紫外線熱處理後，隨紫外線熱處理時間和溫度的增加，薄膜材料結構改變，(CHx / Si-O)的波鋒比(peak area ratio) 與 (Si-CH3 / Si-O) 的波鋒比(peak area ratio)逐漸減少。薄膜性質方面，紫外線熱處理時間的增加，孔隙度亦隨之增加。介電性質方面，適當的紫外線熱處理時間，可以使薄膜介電常數急速降低，而過長的紫外線熱處理時間，將導致薄膜介電常數的上升。機械性質方面，隨著紫外線熱處理時間的增加，薄膜楊格係數、硬度也隨之增加。本研究中利用固定350奈米厚度的薄膜在紫外線熱處理其最佳化的參數是溫度為400°C、時間為8分鐘，使得多孔性介電薄膜獲得較低的介電常數(2.57)和符合元件之機械特性(楊格係數為8.262GPa)可將之應用於45奈米及以下積體電路元件之內層導線之導體。

As ultra large scale integrated (ULSI) circuits shrink to sub-micron dimensions, the interconnect widths become smaller; therefore, signal propagation delays become a dominant part of the overall chip delay. Crosstalk and power consumption greatly increase due to non-compatibility of the parasitic capacitance of interlayer dielectrics and the resistance of wiring metals. To solve this issue, two materials introduced into the multi-layer interconnection of the integrated circuit (IC) device. One is low dielectric material (low capacity), and the other one is copper contact line (low resistitivity).
In this thesis, we focus on investigating the dielectric materials in interconnection of IC devices. There are two ways to introduce porosity into low-k dielectrics to reduce the dielectric constant in current interconnections during semiconductor fabrication. One approach is to introduce terminating bonds, such as Si-H or Si-(Me)n (where Me is represented as a methyl group), incorporated into the Si-O backbone, named “constitutive porosity”, which is formed through self-organization of the materials. The porosity of this low-k material is relatively low, with pore sizes of about 10 A° in diameter. The other approach is a novel and advanced technology that uses a hybrid material, consisting of a Si-O containing matrix and a sacrificial organic porogen (ie. a pore generating material), co-deposited to form a dielectric film; the porogen is then thermally decomposed and removed, thus creating porosity in the film. This porosity is formed subtractively, named “subtractive porosity”. Subtractive porous materials are formed through the selective removal of parts of the volume of the material. The porosity in such material is relatively high, and the pore sizes are about several nanometers in diameter.
The first kind of the low-k dielectrics in our research is so-called “constitutive porosity” low-k materials. In this section, we focused on the studies of properties of a PECVD grown SiOCH film with varying the deposition pressures. Moreover, to study the properties of a PECVD SiOCH films with or without a plasma treatment after optimaling a PECVD SiOCH dielectric. The uses of O2/CO mixture gas and NH3 plasma post-treatment are employed on the as-deposited SiOCH films. These plasma treatments are applied to enhance the resistance of moisture absorption in an as-deposited SiOCH film. The results show the promising properties of such a low-k material as deposition pressure of 2.5 Torr, with a leakage current of 6.455×10-9A/cm2, mechanical strength as in Young’s modulus of 19.26 GPa and hardness of 3.12 GPa, can be expected to be successfully developed. The formation of a SiOx interfacial capping layer using an O2/CO gas ratio of 0.75 and a oxy-nitride film using NH3 gas of 60 sccm on the hybrid-type low k dielectric material to increase the ability of moisture resistance on the SiOCH film with nearly the same dielectric properties can be used in ULSI application
The second kind of the low-k dielectrics in our investigation is so-called “subtractive porosity” low-k materials.Ultra violet (UV) curing process is developed for the optimal processing of such a porous low dielectric material. It’s the brand new concept to apply the UV curing process on copper/low-k interconnects in IC technology. We have made a systematic research of the UV curing process on the SiOCH film and optimized the parameters of the thin film processing. In our work, the effect of the UV curing time and temperature on the thin film of the low dielectric material, SiOCH, is extensively investigated in the Cu/low-k interconnect processing. The bonding of the SiOCH film is characterized by FTIR. The FTIR results show that peak area ratio of CHx/Si-O and Si-CH3/Si-O decrease with the increment of the time and temperature of the UV curing process. The dielectric constant is examined with a metal-insulator- semiconductor (MIS) structure. The dielectric constant will decrease drastically with the time of the UV curing in the first, however, it will increase for longer curing time. Hence, an optimization of the UV curing temperature of 400°C and the time of 8 min is necessary for such a porogen-low-k material. The results show a high performance porous low-k film of k=2.57 and Young’s modulus of 8 GPa, now is developed to improve the mechanical properties of this porous low-k film.

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