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研究生：	古耀揚 Ku, Yao-Yang
論文名稱：	使用 Hartmann-Nazarov 解碼演算法作渦輪積碼的硬體實現 Hardware Implementation of Turbo Product Code Using Hartmann-Nazarov Decoding Algorithm
指導教授：	蘇賜麟 Su, Szu-Lin
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系碩士在職專班 Department of Electrical Engineering (on the job class)
論文出版年：	2004
畢業學年度：	92
語文別：	中文
論文頁數：	51
中文關鍵詞：	渦輪積碼
外文關鍵詞：	Product Code, Hartmann-Nazarov decoding algorith
相關次數：	點閱：54 下載：1
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　　本論文提出一種使用延展型編碼建構的積碼, 作疊代解碼的過程. 這個過程使用一種理想化位元接位元的解碼演算法. 這個解碼規則是基於兩篇論文中所提出的解碼演算法而來: 其中一篇是Carlos R.P. Hartmann及Luther D. Rudolph於1976年所提出的論文, 名稱是“An optimum symbol-by-symbol decoding rule for linear codes”; 另外一篇是L.E. Nazarov 及 V.M. Smolyaninov於1998年所提出的文章, 名稱是“Use of fast Walsh-Hadamard transformation for optimal symbol-by-symbol binary block-code decoding”. 這個規則的複雜度和碼率成反比, 使得這個演算法在高碼率的應用上引人注意. 本文內容先敘述解碼演算法過程, 不同碼率的BER曲線模擬結果描繪於後. 編碼以及疊代解碼過程的硬體實現皆在 DSP TMS320C6711上執行, 其中使用固點運算法.

　　An iterative decoding process of extended product codes is presented. It uses an optimal symbol-by-symbol decoding algorithm. The decoding rule is based on the decoding algorithm presented in two papers: one is the “An optimum symbol-by-symbol decoding rule for linear codes” presented by Carlos R.P. Hartmann and Luther D. Rudolph In 1976; and the other is the “Use of fast Walsh-Hadamard transformation for optimal symbol-by-symbol binary block-code decoding” presented by L.E. Nazarov and V.M. Smolyaninov in 1998. The complexity of this rule varies inversely with code rate, making this algorithm attractive for high rate codes. After the presentation of decoding algorithm, some simulation results of BER are shown with different code rates. The coder and iterative decoding process are implemented on DSP TMS320C6711 using fixed-point arithmetic.

Abstract                                                                   i
Content                                                                   ii
List of Table                                                            iii
List of Figure                                                            iv
Chapter 1  Introduction                                                    1
Chapter 2  The Product Codes                                               2
    2.1 Construction of product codes......................................2
    2.2 Parameters of product codes........................................3
    2.3 Encoding of BCH codes..............................................4
    2.4 Example of product code............................................9
Chapter 3  The Decoding Algorithm                                         13
    3.1 The decoding rule of Hartmann-Rudolph algorithm...................13
    3.2 The binary case of Hartmann-Rudolph decoding rule.................15
    3.3 The decoding rule of Nazarov-Smolyaninov algorithm................17
    3.4 Computation of Nazarov-Smolyaninov decoding rule..................20
Chapter 4  The Iterative Decoding Procedure                               22
    4.1 Iterative Process.................................................22
    4.2 Proof of parity-check theorem.....................................24
Chapter 5  Extended Codes and Modulation                                  28
    5.1 Coding and decoding of extended product codes.....................28
    5.2 The error probability of block code and product code..............30
    5.3 The error probability of QPSK transmission........................33
    5.4 The error probability of 16-QAM transmission......................35
    5.5 Theoretical Calculation and Simulation Result.....................36
        5.5.1 BER calculation.............................................37
        5.5.2 BER simulation result.......................................40
    5.6 Simulation Conclusion.............................................42
Chapter 6  Hardware Implementation                                        43
    6.1 Fixed-Point Setting...............................................46
    6.2 Mathematical functions computation................................46
    6.3 Test Result.......................................................48
Chapter 7  Conclusion                                                     49
Bibliography                                                              50

                                    

[1] André Goalic, Karine Cavalec-Amis and Vincent Kerbaol, “Real-time turbo
decoding of block turbo codes using the Hartmann-Nazarov algorithm on the DSP
TEXAS TMS320C6201,” Départment Signal et Communications, 2002.

[2] Carlos R. P. Hartmann and Luther D. Rudolph, “An optimum symbol-by-symbol
decoding rule for linear codes,” IEEE Trans. on Information Theory, Vol.
IT-22, No. 5, pp.514-517, September 1976.

[3] L.E. Nazarov and V.M. Smolyaninov, “Use of fast Walsh-Hadamard
transformation for optimal symbol-by-symbol binary block-code decoding,”
Electronics Letters, Vol. 34, No. 3, pp.261-262, February 1998.

[4] Mischa Schwartz, “Information Transmission, Modulation, and Noise” Chapter
5 and 6, Third Edition, Printed in Taiwan by The Southeast Book Company by
Special Agreement with McGraw-Hill International Book Company, 1981.

[5] Shu Lin and Daniel J. Costello, Jr., “Error Control Coding – Fundamentals
and Applications,” Chapter 2-6, Printed in U.S.A, by Prentice-Hall, Inc.,
1983.

[6] Texas Instruments, “TMS320C6000 CPU and Instruction Set Reference Guide”,
SPRU189F, Printed in U.S.A., October 2000.

[7] Texas Instruments, “TMS320C6000 Peripherals Reference Guide”, SPRU190C,
Printed in U.S.A., April 1999.

[8] Texas Instruments, “TMS320C6000 DSP/BIOS User’s Guide”, SPRU303, Printed
in U.S.A., May 1999.

[9] W. Rudin, Fourier Analysis on Group. New York: Wiley, 1967.

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校外：2004-07-30公開

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