本論文主要研製24與60 GHz CMOS射頻開關及3-10 GHz CMOS超寬頻低雜訊放大器。60-GHz收發開關晶片製作使用國家晶片中心(CIC)提供之TSMC CMOS 0.13 μm製程，而24-GHz射頻收發開關與3-10 GHz超寬頻低雜訊放大器採用TSMC CMOS 0.18 μm製程製作。
60-GHz CMOS收發開關採用基極浮接架構。量測結果顯示：在57-64 GHz頻段內，直流偏壓為1.2V(ON) / 0V (OFF)、總消耗功率約為0 mW、天線端反射損失10.8-13.5 dB、Rx反射損失14.7-20.6 dB、Tx端反射損失12.3-17.4 dB、Rx端插入損耗為8.1-8.7 dB、隔離度26.6-28.6 dB，Tx端插入損耗為8.2-9.2 dB、隔離度28.2-31.7 dB。 IP1dB為11 dBm、IIP3為18.4 dBm。24-GHz CMOS收發開關採用基極浮接與洩漏訊號消除架構。量測結果顯示：在24 GHz，直流偏壓為1.2 V / 0V、天線端反射損失大於13.3 dB、Rx反射損失大於12.8 dB、Tx端反射損失大於12.6 dB、Rx端插入損耗為7.3 dB、Tx端插入損耗為7.4 dB、Rx與Tx端隔離度為34.3 dB。IP1dB為18 dBm、IIP3為28.5 dBm。3-10 GHz超寬頻低雜訊放大器採用並-並式電阻回授與源極退化電感方式進行設計，並-並式電阻回授有助於輸入匹配的實現與雜訊的設計。量測結果顯示：在3.1-10.6 GHz之頻段，直流偏壓為1.0 V/15.0 mA，輸入反射損失大於13.8 dB，輸出返射損耗大於13.2 dB，增益為6.1-10.5 dB，隔離度大於31.2 dB，IP1dB為-15.8 - -7.4 dBm，IIP3為-4-2.8 dBm，雜訊指數為4.1-5.3 dB。3dB頻寬處，為3.1-9 GHz，功率增益為7.5-10.5 dB，雜訊指數為4.1-5 dB，IP1dB為-15.8--9 dBm，IIP3為-4–1.5 dBm。

This thesis presents the design of a 24 and 60 GHz CMOS T/R switches and a 3-10 GHz CMOS UWB low-noise amplifier (LNA). The 60 GHz T/R switch are fabricated with TSMC CMOS 0.13-μm process. In addition, The 24 GHz T/R switch and 3-10 GHz UWB LNA are fabricated with TSMC CMOS 0.18-μm process. The 60 GHz CMOS T/R switch adopts the body-floating technology. The 24 GHz CMOS T/R switch utilizes the leakage cancellation and body-floating technologies. The 3-10 GHz UWB LNA uses the resistive shunt feedback and source degeneration inductor to achieve a good input return loss and low noise figure.

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