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研究生：	陳映璁 Chen, Ying-Tsung
論文名稱：	利用高介電係數電介質/金屬閘極結合化學氧化物的整合結構去達到高效能的20奈米n型及p型金屬氧化物半導體元件 Using High-K Dielectric/Metal Gate with the Chemical Oxide Integration Scheme to Achieve High Performance 20-nm n/pMOS Devices
指導教授：	張守進 Chang, Shoou-Jinn
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 微電子工程研究所 Institute of Microelectronics
論文出版年：	2014
畢業學年度：	102
語文別：	英文
論文頁數：	115
中文關鍵詞：	高介電係數、界面層、等效氧化物厚度、沉積後退火、矽酸鉿、分耦式電漿氮化
外文關鍵詞：	High-K (HK), Interfacial layer (IL), Equivalent oxide thickness (EOT), post-deposition annealing (PDA), Hf-Silicate (HfSiO), Decoupled Plasma Nitridation (DPN)
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為了達到高效能的20 奈米金屬氧化物半導體（Metal-Oxide-Semiconductor, MOS）元件之目標，金屬氧化物半導體的電介質材料和閘極長度需要持續不斷地薄化和微縮，然而當閘極電介質厚度變薄時，其絕緣能力也會隨之變差，閘極漏電流也會隨之而增加。因此高介電係數電介質材料被使用來降低閘極漏電流。而金屬閘電極的平帶電壓和等效功函數容易受到材料本質特性和高溫回火製程的限制和影響而退化至矽能帶中間，故高介電係數電介質/金屬閘極 (High-K dielectric/Metal gate) 的製程技術需要不斷的進步。本論文主要是分成四個部份去探討後高介電質/後金屬閘電極 (High-K-last/gate last) 結合化學氧化物界面層的製程整合結構，其研究方向著重於如何去獲得高效能的20 奈米n 型及p 型金屬氧化物半導體元件。
首先，本論文呈現後高介電質/後金屬閘電極結合熱氧化物的整合結構能較前高介電質/後金屬閘電極結合熱氧化物的整合結構在20 奈米製程下能獲得較薄的等效氧化物厚度。雖然如此，其仍無法滿足20 奈米等效氧化物厚度薄化的要求。故本論文進一步地去使用化學氧化物取代熱氧化物來當作高介電係數電介質和矽之間的界面層。由實驗結果可知高介電係數電介質/化學氧化物界面層間會產生矽氧化鉿(Hf-silicate, HfSiO)元素層，這個矽氧化鉿物質可以提供較高的等效介電係數而進一步去得到較薄的等效氧化物厚度。
但是化學氧化物界面層結構較熱氧化物界面層為鬆散，對元件來說，會增加其漏電徑，而造成閘極漏電流的上升。也就是說，化學氧化物界面層的閘極漏電流較熱氧化物界面層大，其中，n 型金屬氧化物半導體元件尤其顯著。因此，本論文進一步的提出利用沉積後退火處理製程來改善高介電質/化學氧化物界面層的品質而進一步地去降低閘極的漏電流，同時也討論何種氣體 (氧氣、氨氣、氮氣、氧氣＋氨氣) 的沉積後退火處理製程能夠較有效的來降低因使用化學氧化物界面層所增加的閘極漏電流。實驗的分析結果顯示氧氣的沉積後退火處理製程能夠較其它氣體更為有效的降低閘極漏電流。而因使用氧氣沉積後退火處理製程所增加的等效氧化物厚度也可以藉由優化n 型及p 型功函數金屬來薄化。
為了更進一步地去薄化n 型及p 型金屬氧化物半導體元件的等效氧化物厚度，在後高介電質/後金屬閘電極結合化學氧化物的整合結構下，本論文將沉積後退火處理製程改由分耦式電漿氮化結合後氮化退火處理製程來形成氮氧矽鉿化合物 (HfSiON)元素層，並達成等效氧化物厚度薄化的目的。並且由實驗結果發現低濃度的氮氣體結合高溫的後氮化退火處理製程，其所表現的平帶電壓和金屬公函數以及閘極漏電流與使用氧氣沉積後退火處理製程最為接近，p 型金屬氧化物半導體元件的平帶電壓只比其稍為退化一點，但卻能得到符合20 奈米元件的等效氧化物厚度薄化需求。
最後，在後高介電質/後金屬閘電極結合化學氧化物的整合結構搭配氧氣沉積後退火處理製程下，本論文進一步地提出利用原子層沉積 (Atomic Layer Deposition,ALD) 技術去取代物理氣相沉積來沉積氮化鈦阻擋層。並由能量散佈光譜儀 (EDS)來分析金屬閘電極的剖面元素成分，藉以驗証原子層沉積氮化鈦阻擋層可以較物理氣相沉積所沉積氮化鈦阻擋層更能有效地抑制氧過度的從鉿基料高介電質/界面層擴散。並由電性結果發現較厚原子層沉積的氮化鈦阻擋層不但能有效地降低p 型金屬氧化物半導體元件的閘極漏電流，而且比物理氣相沉積氮化鈦阻擋層更能有效的薄化其等效氧化物厚度。除此之外，也能夠獲得更接近p 型金屬氧化物半導體元件平帶電壓的理想值。本論文說明了後高介電質/後金屬閘電極結合化學氧化物的整合結構，並深入的探討如何改善20 奈米n 型及p 型金屬氧化物半導體元件的效能。

In order to achieve the purpose of high performance metal-oxide-semiconductor (MOS) devices of 20-nm technology node, the dielectric material and gate length of MOS devices are must continuously thinning and scaling down. However, the gate leakage current density (Jg) is also enhanced by thinner thickness and worse insulation capability of gate dielectric. For this reason, high-K dielectric materials were introduced to reduce the gate leakage current density. Nevertheless, the flat band voltage (Vfb) and effective work function (EWF) of metal gate electrode are easily degraded to silicon middle band gap that induced by material intrinsic characteristic limit and high temperature activation steps. Consequently, the technology of higk-K dielectric/metal gate (MG) needs nonstop progress to overcome this issue. This dissertation is divided into four main parts to study the high-K-last/gate-last with the chemical oxide interfacial layer (IL) integration scheme, and this thesis focuses on the how to obtain high performance nMOS and pMOS devices of 20-nm technology node.
In first investigate, this dissertation presents that the high-K-last/gate-last integration scheme involving the use of a thermal oxide interfacial layer (IL) could provide more thinner equivalent oxide thickness (EOT) than high-K first/gate-last with a thermal oxide integration scheme in 20-nm technology node. Even though, it is still difficult to further thin down EOT to meet the demand of high performance and low power for 20-nm technology node. This dissertation has proposed a high-K-last/gate-last integration scheme with a chemical oxide interfacial layer (IL) to meet EOT thin down requirement. It was found that chemical oxide IL could form Hf-silicate (HfSiO) element at the high-K/IL interface so as to provide us a larger effective K value and a smaller equivalent oxide thickness. It was also found that the larger gate leakage current density for the samples with chemical oxide IL could be effectively suppressed by post-deposition annealing (PDA)treatment. In another word, the PDA treatment was used to improve the performances of high-K-last/gate-last integration scheme with a chemical oxide IL. Furthermore, it was found that PDA treatment induced larger EOT could be reduced by optimizing the metal gate stack. It was also found that we could achieve small gate leakage current density and minimal flat-band voltage (Vfb) degradation of nMOS and pMOS devices by PDA treatment in O2 atmosphere. Furthermore, it was found that equivalent oxide thickness,
gate leakage current density and flab-band voltage could be further improved by optimizing the metal gate stack.
In order to further to thin down the EOT, this dissertation presents used a decoupled plasma nitridation (DPN) with post-nitridation annealing (PNA) treatment method to improve and enhance the performances of nMOS and pMOS devices with high-K-last/gate-last integration scheme and chemical oxide IL. By introducing N to form HfSiON, it was found that DPN with appropriate PNA treatments could provide smaller equivalent oxide thickness for both nMOS and pMOS devices. It was also found that we could achieve thebest overall device performance for the high-K-last/gate-last integration scheme with a chemical oxide IL by introducing lower percentage nitrogen gas content during DPN followed by higher temperature PNA.
In last study, this dissertation propose the use of the atomic layer deposition (ALD) TiN barrier metal to replace the physical vapor deposition (PVD) TiN barrier meyal on high-K-last/gate-last pMOS devices with a chemical oxide interlayer in 20-nm technology node. And the Energy Dispersive Spectrometer (EDS) was used to analyze the element distributes of cross-section of metal gate electrode for verifying the ALD TiN barrier metal which could effectively suppress oxygen out-diffusion from the high-K/IL stack. It was found that the pMOS devices with ALD TiN barrier metal exhibit lower gate leakage current density and thinner equivalent oxide thickness. Furthermore, it was found that wecould achieve larger flat band voltage (Vfb) and larger equivalent work function (EWF) from the pMOS devices with ALD TiN barrier metal. It was also found that we could further improve the performances of the fabricated pMOS devices by increasing the ALD TiN thickness.

Contents
Abstract (Chinese)	II
Abstract (English)	V
Contents	VIII
Table captions	X
Figure captions	XI
Chapter 1 Introduction	1
1 Background of High-K/Metal Gate Process and Related Development	1
2 Organization of This Dissertation	3
Chapter 2 Relevant Theory and Experimental Equipment	10
1 Introduction	10
2 Theory of Capacitance–Voltage (C–V) Extraction                               11
3 EOT, Vfb and EWF Extraction                                          11
4 Experimental Equipment of MOSCAP Process	14
4.1 Metal Sputtering Equipment Introduction	14
4.2 Atomic Layer Deposition (ALD) System Introduction	14
4.3 Rapid Thermal Process (RTP) Introduction	14
4.4 Decoupled Plasma Nitridation (DPN) Process Introduction	14
5 The Analysis of MOSCAP Structure	17
5.1 High-Resolution Transmission Electron Microscopy (HRTEM) Equipment Introduction                                      	17
5.2 Energy Dispersive Spectrometer (EDS) Technology Introduction	 17
5.3   Angular Resolved X-ray Photoelectron Spectroscopy (ARXPS) Technology Introduction	 18
Chapter 3 Metal-Oxide-Semiconductor Capacitor (MOSCAP) Test Structure Design and Fabrication                                                           37	
1 Introduction	37
2 MOSCAP Test Structure Design	39
3 MOSCAP Test Structure Fabrication Introduction	39
Chapter 4 Chemical Oxide Interfacial Layer (IL) for the High-K-Last/Gate-Last Integration Scheme	53
1 Introduction	53
2 Experimentation Design and Devices Fabrication	55
3 Physical and Electrical Characteristics of Interfacial Layer (IL)	56
4 Effects of Post-Deposition Annealing (PDA) Treatment	59
5 Summary	61
Chapter 5 Effects of DPN with PNA Treatment for High-K Stacks with Chemical Oxide Interfacial Layer	73
1 Introduction	73
2 Experimentation Design and Devices Fabrication	74
3 Electrical and Physical Investigations of DPN with PNA Treatment	75
3.1 Electrical Characteristics of DPN with PNA Treatment	75
3.2 Physical Characteristics of DPN with PNA Treatment	77
4 Summary	78
Chapter 6 ALD TiN Barrier Metal for pMOS Devices with a Chemical Oxide Interfacial Layer for 20-nm Technology Node	86
1 Introduction	86
2 Experimentation Design and Devices Fabrication	87
3 Electrical and Physical Investigations of TiN Barrier Metal	88
3.1 Electrical Characteristics of TiN Barrier Metal	88
3.2 Physical Characteristics of TiN Barrier Metal	90
4 Summary	91
Chapter 7 Conclusion and Future Work	97
1 Conclusion	97
2 Future Work	98
Abstract (Chinese)	II
Abstract (English)	V
Contents	VIII
Table captions	X
Figure captions	XI
Chapter 1 Introduction	1
1 Background of High-K/Metal Gate Process and Related Development	1
2 Organization of This Dissertation	3
Chapter 2 Relevant Theory and Experimental Equipment	10
1 Introduction	10
2 Theory of Capacitance–Voltage (C–V) Extraction                               11
3 EOT, Vfb and EWF Extraction                                          11
4 Experimental Equipment of MOSCAP Process	14
4.1 Metal Sputtering Equipment Introduction	14
4.2 Atomic Layer Deposition (ALD) System Introduction	14
4.3 Rapid Thermal Process (RTP) Introduction	14
4.4 Decoupled Plasma Nitridation (DPN) Process Introduction	14
5 The Analysis of MOSCAP Structure	17
5.1 High-Resolution Transmission Electron Microscopy (HRTEM) Equipment Introduction                                      	17
5.2 Energy Dispersive Spectrometer (EDS) Technology Introduction	 17
5.3   Angular Resolved X-ray Photoelectron Spectroscopy (ARXPS) Technology Introduction	 18
Chapter 3 Metal-Oxide-Semiconductor Capacitor (MOSCAP) Test Structure Design and Fabrication                                                           37	
1 Introduction	37
2 MOSCAP Test Structure Design	39
3 MOSCAP Test Structure Fabrication Introduction	39
Chapter 4 Chemical Oxide Interfacial Layer (IL) for the High-K-Last/Gate-Last Integration Scheme	53
1 Introduction	53
2 Experimentation Design and Devices Fabrication	55
3 Physical and Electrical Characteristics of Interfacial Layer (IL)	56
4 Effects of Post-Deposition Annealing (PDA) Treatment	59
5 Summary	61
Chapter 5 Effects of DPN with PNA Treatment for High-K Stacks with Chemical Oxide Interfacial Layer	73
1 Introduction	73
2 Experimentation Design and Devices Fabrication	74
3 Electrical and Physical Investigations of DPN with PNA Treatment	75
3.1 Electrical Characteristics of DPN with PNA Treatment	75
3.2 Physical Characteristics of DPN with PNA Treatment	77
4 Summary	78
Chapter 6 ALD TiN Barrier Metal for pMOS Devices with a Chemical Oxide Interfacial Layer for 20-nm Technology Node	86
1 Introduction	86
2 Experimentation Design and Devices Fabrication	87
3 Electrical and Physical Investigations of TiN Barrier Metal	88
3.1 Electrical Characteristics of TiN Barrier Metal	88
3.2 Physical Characteristics of TiN Barrier Metal	90
4 Summary	91
Chapter 7 Conclusion and Future Work	97
1 Conclusion	97
2 Future Work	98
Reference	101
                                    

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