本論文研製毫米波CMOS寬頻可變增益低雜訊放大器及使用前置失真線性器之94-GHz CMOS功率放大器，採用TSMC CMOS 0.18-μm製程或90-nm GUTM製程進行設計。12–25 GHz CMOS寬頻可變增益低雜訊放大器以電流控制機制(current steering)來控制電晶體轉導值使其主體電流產生變化以達增益之調控；寬頻設計的部份則利用電阻式回授的方式並加上額外之電感、電容來做為匹配網路。50–67 GHz CMOS寬頻可變增益放大器此架構的可變增益設計以及寬頻設計的部份與12–25 GHz CMOS寬頻可變增益低雜訊放大器設計類似，主要差異為:此寬頻放大器中額外使用了增益強化(gain boosting)電感來增加整體的增益表現，同時額外多使用一個輸出緩衝器(test buffer)來作為輸出端的寬頻匹配元件與提升增益之用。使用前置失真線性器之94-GHz CMOS功率放大器設計上採用串接四級common-source (CS)的cascode架構來提高增益輸出以減輕PA前端輸入電路的負擔，而為加強電路的線性度特性，此架構使用一線性器來強化IP1dB特性，同時級間匹配採用能達到較小面積的匹配網路以利系統整合。電路設計以Agilent ADS與Ansoft 3-D全波電磁模擬軟體HFSS進行模擬，量測部分則是採用on-wafer方式進行，根據欲量測特性之不同，相關量測方式亦有所調整。

This thesis presents the research on millimeter-wave (MMW) CMOS wideband variable-gain low-noise amplifiers (VG-LNAs) and a 94-GHz CMOS power amplifier (PA) with built-in pre-distortion linearizer, implemented by standard TSMC 0.18-μm or 90-nm GUTM CMOS process. To obtaine wideband frequency response, the resistive-feedback skill with additional passive components is used as the matching network. In the 60-GHz VG-LNA design, a gain boosting inductor is used in order to obtain a better gain performance. In 94-GHz CMOS PA design, a four stage CS cascade structure is adopted for output gain enhancement. Futhermore, the linearity performance of designed PA such as IP1dB is improved by the built-in pre-distortion linearizer. The measured performances of the designed MMW CMOS RFICs are all performed by using the on-wafer measurement. Simulation and measurement results are compared and discussed.

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