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研究生: 蔡玉嫻
Tsai, Yu-Hsien
論文名稱: 應用於行人偵測之梯度方向直方圖硬體實作
The VLSI Implementation of Histograms of Oriented Gradients for Human Detection
指導教授: 陳培殷
Chen, Pei-Yin
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2011
畢業學年度: 99
語文別: 中文
論文頁數: 56
中文關鍵詞: 行人偵測梯度方向直方圖VLSI硬體實現
外文關鍵詞: human detection, histograms of oriented gradients, VLSI
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  • 近幾年來,行人偵測技術一直都是電腦視覺領域中廣受重視的議題。在行車輔助系統及監視系統等應用中,準確的行人偵測技術有助於人身安全保障的提升。然而,要克服行人偵測的種種挑戰,需仰賴可靠的特徵擷取演算法。梯度方向直方圖(HOG)是一個密集類型的特徵擷取方法,它對行人外形多樣貌、行人姿態多變性、影像光線干擾等辨識上的障礙,皆有著突破性的優異效果。由於HOG方法複雜需要很長的運算時間,因此本論文希望設計一個梯度方向直方圖VLSI硬體電路,讓即時的行人偵測變成可能。
    我們使用近似的方式,將梯度方向直方圖演算法中難以使用硬體實作的複雜運算,如:平方和開根號、反正切函式、開根號倒數等,實現成電路。所提出的梯度方向直方圖電路架構,除了適用於低成本硬體實現之外,還同時具備較高的工作效率。
    我們使用Verilog硬體描述語言來實作所提出的17級管線梯度方向直方圖VLSI架構。根據SYNOPSYS的Design Compiler及Artisan TSMC 0.13μm標準元件庫的電路合成結果,該電路需要153K個邏輯閘數,工作時脈可以達到167MHz,吞吐量(throughputs)則為每秒6012x106個向量,平均每秒可以處理1641張WQSXGA (3200×2048)大小的畫面。與其他硬體實作的論文相比,我們的電路成本較低且能在較短的時間內處理完一張待辨識的圖片,並維持高達95%的行人正確辨識率。

    In recent years, human detection has been widely discussed in computer vision. In the applications of driver assistant and surveillance systems, human detection technology is the most important. To overcome the challenges of human detection, we need a reliable feature extraction algorithm. Histograms of Oriented Gradients(HOG) is a very efficient feature extraction algorithm and attracts more and more attention recently. It achieves excellent results to break through the obstacles, such as the diversity of human appearance, the variance of human poses and the interference of an image due to the light changing. However, HOG requires high computational time, so we think that it is worthy to design the HOG VLSI architecture for real-time applications.
    In HOG, many operations, such as square root for sum of squares, arctangent, and inverse square root, are difficult to be realized with hardware circuit. Using some approximate methods to replace the complex operations, we develop a low-cost and fast circuit in this thesis.
    The 17 stages pipelined hardware architecture for the proposed design is implemented by using Verilog and synthesized with SYNOPSYS Design Compiler in TSMC 0.13μm cell library. The circuit needs 153K gate counts, and achieves 167 MHz. The throughputs are 6012x106 vectors per second, so that we can process 1641 images with 3200x2048 pixels per second. The accuracy rate of our circuit for human detection is higher than 95%.

    第一章 緒論……………………………………………………………………1 1.1 研究背景………………………………………………………………..1 1.2 研究動機和方向………………………………………………………..2 1.3 論文組織………………………………………………………………..3 第二章 相關演算法……………………………………………………………4 2.1 行人偵測之流程..…….………………………………………………...4 2.2 梯度方向直方圖…….………………………………………………….6 2.3 支援向量機介紹..…….…………………………………………….…14 第三章 所提出的硬體實作方法…………………………………………….16 3.1 梯度強度計算…….….………………………………………………..16 3.2 梯度方向計算………..………………………………………………..17 3.3 梯度強度權重分配….….……………………………………………..19 3.4 正規化計算………….….……………………………………………..20 第四章 VLSI硬體實現……………………………………………………….25 4.1 硬體實作之系統架構…..……………………………………………..25 4.2 管線化架構與平行處理設計….….…………………………………..29 第五章 實驗結果……………………………………………………………...42 5.1 模擬環境………………..……………………………………………..42 5.2 模擬結果……………..………………………………………………..44 5.3 比較與驗證…………..………………………………………………..50 第六章 結論與未來工作……………………………………………………...54 6.1 結論………………..…………………………………………………..54 6.2 未來工作…………..…………………………………………………..54 參考文獻………………………………………………………………………..55

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