近年來，隨著物聯網以及人工智慧的快速發展，龐大資料量需要運算。為了解決遠端傳輸、用戶隱私等問題以及加快人工智慧運算的速度，邊緣運算裝置的需求也逐漸上升。其中低功耗、低延遲的需求對邊緣裝置尤為重要。由記憶體組成的記憶體陣列，可將計算與儲存同時進行達成「記憶體內運算」，並具備平行化處理大量矩陣運算的能力， 成為近年來熱門的研究項目。
記憶體陣列的選擇中，隨機存取記憶體具有可高速運算及製程穩定的優勢，然而主要問題仍在如何降低其待機時漏電流造成的功耗。鐵電非揮發性隨機存取記憶體的設計在現有的製程步驟上，後端製程加上鐵電電容、使用電壓操作的方式記憶，讓原本無法關閉、需要待機的隨機存取記憶體，在重新開啟電源後可順利快速回復資料。
本文使用L-K以及NLS兩種鐵電等效模型，依其計算理論萃取實際量測的鐵電電容特性參數，並擇優以模擬Nv-SRAM元件，證明在低電壓時選擇適當的操作方式，使得Nv-SRAM有更好的寫入及資料回復的穩定性，並且此操作方式，元件面積縮小時依然有良好的表現，達成邊緣運算裝置微縮的需求。

With the rapid development of the Internet of Things (IoT) and artificial intelligence (AI) in recent years, fast computation of huge bulks of data is required. To solve issues such as remote-end transmission, user privacy, etc., and to increase the speed of AI computation, there is a rising demand for edge-computing devices, and low power consumption and low delay requirements for edge-computing devices have become more and more important. As memory arrays composed of memories can perform computation simultaneously with storage to achieve computing-in-memory (CIM) and are capable of parallel processing of bulk matrix computation, they have become popular topics of research in recent years.
Of various memory array options, static-random-access-memory (SRAM) has the advantages of fast computation and stable processing. However, there is a major problem with SRAM which lies in how undesirable power consumption caused by standby leakage current can be reduced. For the design of ferroelectric non-volatile SRAMs in existing processing methods, a ferroelectric capacitor is employed in backend process, and the memory function is achieved by voltage operation, so that SRAMs which originally have to be in a standby mode can smoothly recover data after power is turned on again.
In this study, two kinds of ferroelectric compact models, L-K model and NLS model, were used and measurements of ferroelectric capacitor characteristic parameters were extracted based on their calculation theories. The one with better time response was selected to perform simulation of Nv-SRAM cell to demonstrate that by selecting an appropriate operating method during low voltage, Nv-SRAM has better write and data recovery stability, and that such operating method still has a satisfactory performance with a reduced size element, thereby allowing for scaling of edge-computing devices.

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