| 研究生: |
馬清軒 Ma, Ching-Hsuan |
|---|---|
| 論文名稱: |
影像邊緣保留摺積插補演算法之設計與實現 An Efficient VLSI Implementation of an Edge-Preserving Convolution Interpolation for Digital Images |
| 指導教授: |
陳培殷
Chen, Pei-Yin |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年: | 2010 |
| 畢業學年度: | 98 |
| 語文別: | 中文 |
| 論文頁數: | 54 |
| 中文關鍵詞: | 影像縮放 、影像插補 、邊緣保留 、VLSI 硬體實現 |
| 外文關鍵詞: | image scaling, interpolation, edge-preserving, VLSI |
| 相關次數: | 點閱:169 下載:8 |
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影像縮放演算法在影像處理中,是一個十分重要的技術,常使用在來源影像之解析度不同於目標顯示裝置上之解析度時。在實際的應用裡,一般是將影像縮放的程序放在終端使用者裝置內,例如:可攜式媒體播放器、高解析度電視、液晶電視、數位錄放影機以及影印機…等日常生活中常見的即時顯示設備。
本論文提出了一個新的影像插補演算法-邊緣保留插補演算法(EPI)。此方法以數值分析中常用的插補誤差理論為基礎,發展線性型式邊緣保留插補(EPI)函數,並推導出邊緣保留核心,最後組合此邊緣保留核心與摺積運算為摺積型式EPI演算法。實驗結果證明,在相似複雜度的演算法中,EPI能有效地保留縮放後的影像邊緣,具有更好的客觀數據以及主觀視覺品質。然而我們所提出的演算法還有低計算複雜度的特性,因此非常適合以VLSI硬體實現。
針對所提出的演算法,我們設計了一個高效能的九級管線化硬體架構,並用Verilog硬體描述語言實現。根據SYNOPSYS的Design Compiler與TSMC 0.18μm的標準元件庫合成的結果,此電路需要的邏輯閘數目為12.9K,工作時脈可以達到200MHz,足夠即時處理目前流行的Full HD或更高解析度格式影片。
Image scaling is a very important technique in image processing. It is indispensable when the resolution of an image generated by a source device is different from the screen resolution of a target display. In many practical real-time applications, the scaling process is included in end-user equipment, such as portable media players, HDTV, LCD-TVs, digital video camcorders, copy-print machines and so on.
This paper presents a new interpolation method, called the Edge-Preserving Interpolation (EPI), which is based on the interpolation error theorem. We adopt the convolution interpolation kernel to preserve the image edge features effectively. Extensive experimental results demonstrate that our method can obtain better performances in terms of both quantitative evaluation and visual quality than those state-of-the-art image scaling techniques with similar computational complexity. Since the proposed method requires low computational complexity, it is very suitable for real-time hardware implementation.
The VLSI architectures for the proposed design was implemented and synthesized by using Verilog HDL and SYNOPSYS Design Compiler with TSMC 0.18μm cell library. Synthesis results show that the circuit can achieve 200 MHz with 12.9K gate counts. It is quick enough to process a full 1080p (1920×1080) High Definition (HD) video in real time.
[1] S. Fifman, “Digital rectification of ERTS multispectral imagery,” in Proc. Significant Results Obtained from Earth Resources Technology Satellite-1, vol.1, pp. 1131-1142, 1973.
[2] J. A. Parker, R. V. Kenyon and D. E. Troxel, “Comparison of interpolation method for image resampling,” IEEE Trans. Medical Imaging, vol. 2, no. 3, pp. 31-39, 1983.
[3] C.-H. Kim, S.-M. Seong, J.-A. Lee and L.-S. Kim, “Winscale: An image scaling algorithm using an area pixel model,” IEEE Trans. Circuits & Systems for Video Technology, vol. 13, no.6, pp. 549-553, June 2003.
[4] R. G. Keys, “Cubic convolution interpolation for digital image processing,” IEEE Trans. Acoustics, Speech and Signal Process., vol. ASSP-29, no. 6, pp. 1153-1160, Dec. 1981.
[5] J. Allebach and P.-W. Wong, “Edge-directed interpolation,” in Proc. Int. Conf. Image Process., vol. 3, pp. 707–710 , Sept. 1996.
[6] X. Li and M. T. Orchard, “New edge-directed interpolation,” IEEE Trans. Image Process., vol. 10, no. 10, Oct. 2001.
[7] Y. Cha and S. Kim, “The error-amended sharp edge (EASE) scheme for image zooming,” IEEE Trans. Image Process., vol. 16, no. 6, June 2007.
[8] Q. Wang and R. K. Ward, “A new orientation-adaptive interpolation method,” IEEE Trans. Image Process., vol. 16, no. 4, Apr. 2007.
[9] S. Carrato and L. Tenze, “A high quality 2× image interpolator,” IEEE Signal Processing Letters, vol. 7, no. 6, pp. 132-134, June 2000.
[10] E. Catmull and R. Rom, “A Class of Local Interpolating Splines,” in Computer Aided Geometric Design, R. E. Barnhill & R. F. Riesenfeld (eds.), Academic Press, pp. 317–326, 1974.
[11] H. S. Hou and H. C. Andrews, “Cubic splines for image interpolation and filtering,” IEEE Trans. Acoustics, Speech, and Signal Process., vol. ASSP-26, no. 6, Dec. 1978.
[12] I. Andreadis and A. Amanatiadis, “Digital image scaling,” IEEE Instrumentation and Measurement Tech. Conf., vol. 3, pp. 2028-2032, May 2005.
[13] P.-Y. Chen, C.-Y. Lien, and C.-P. Lu, “VLSI Implementation of an edge-oriented image scaling processor,” IEEE Trans. Very Large Scale Integration Systems, vol. 17, no. 9, pp. 1275-1284, Sept. 2009.
[14] R. C. Gonzalez and R. E. Woods, Digital Image Processing, 2nd Edition, NJ: Prentice-Hall, 2002.
[15] J. F. Epperson, An introduction to numerical methods and analysis, John Wiley & Sons, 2007.
[16] S. Thurnhofer and S. Mitra, “Edge-enhanced image zooming,” Opt. Eng., vol. 35, no. 7, pp. 1862–1870, 1996.
[17] H. Kim, S. Jin, S. Yang and J. Jeong, “Enhanced edge-weighted image interpolation algorithm,” in Proc. of 8th Int. Conf. Hybrid Intelligent Systems, pp. 957-958, Sept. 2008.
[18] C.-C. Lin, M.-H. Sheu, H.-K. Chiang, C. Liaw and Z.-C. Wu, “The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing,” IEEE Int. Sympo. Circuits and Systems, pp.480-483, May 2008.