本論文研製CMOS毫米波功率放大器及94-GHz CMOS次諧波單混頻器射頻收發機之整合晶片設計研究，採用TSMC 90-nm GUTM CMOS製程進行設計。使用增益提升技巧之94-GHz CMOS中功率放大器設計上採用串接四級共源極(common source, CS)的疊接(cascode)架構並搭配A類放大器之偏壓形式實現，同時藉由增益提升技巧(gain boosting)的方式使其具有較佳的線性度及功率增益來減輕其它發射機前端電路的設計負擔。使用縮小化3-dB正交耦合器之94-GHz CMOS功率放大器利用TSMC 90-nm GUTM CMOS製程之多層結構特色設計一縮小化耦合器做為功率結合/分波器，用來提升功率放大器之輸出功率以加強發射機系統訊號強度，同時也能改善傳統架構由於面積過大而不利於系統整合的缺點。94-GHz CMOS次諧波單混頻器射頻收發機整合晶片目標為設計一個94-GHz CMOS高增益功率放大器與敝實驗室其它同學設計之射頻收發開關、低雜訊放大器及混頻器進行整合。其發射端及接收端僅採用一個同時具有升頻與降頻功能之混頻器來做使用，中間以收發開關做切換，與傳統架構相比能省下一個混頻器及部份濾波器的使用，進而達到縮小晶片面積的功效，同時也能降低收發機之電路複雜度。電路設計以Agilent ADS與ANSYS 3-D全波電磁模擬軟體HFSS進行模擬，量測部份皆是採用on-wafer方式進行，根據欲量測參數特性之不同，相關量測架設方式亦有所調整。

This thesis presents the research on CMOS millimeter-wave (MMW) medium power amplifiers (PAs) and a 94-GHz CMOS sub-harmonic single-mixer RF transceiver (TRx), implemented by standard TSMC 90-nm GUTM CMOS process. In the 94-GHz CMOS medium power amplifier (MPA) design, a four stage class-A common-source (CS) cascode structure with gain-boosting technique is adopted for linearity and power gain enhancement. In the 94-GHz CMOS balanced PA design, a compact 3-dB miniaturized quadrature coupler is employed as a low-insertion-loss power splitter/combiner to improve the output power and provide an area-efficient solution for balance PA design. In the 94-GHz CMOS single-mixer TRx, a high-gain PA is designed for integrating with T/R switches, a low-noise amplifier (LNA), and a sub-harmonic single up/down conversion mixer. The CMOS TRx uses only one up/down conversion mixer and T/R switches to change the modes between transmitting (Tx) and receiving (Rx) path. Compared with the traditional TRx architecture, it can reduce the chip size without the use of additional mixer and filters, and also simplify the complexity of TRx design. The measured performances of the designed MMW CMOS RFICs are all performed by using the on-wafer measurement. Simulation and measurement results are compared and discussed.

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