FinFET元件因具有三面立體式之閘極結構設計，可增強閘及對通道之控制能力與抑制通道貫穿效應所產生之漏電流，故較相同尺寸傳統MOSFET具有較佳之閘極控制能力。然因FinFET之三面閘極結構易導致通道導電率不均勻分佈，因此於進行FinFET尺寸設計考量上，必需在通道之尺寸比例作縝密之規劃，同時尚須顧及元件驅動能力與低漏電電流之要求。
　　本論文旨在針對鰭狀場效電晶體(FinFET)進行三維電性模擬分析，其中元件結構設計與臨界電壓(VTsat)、汲極引致能障下降(Drain induced barrier lowering, DIBL)、次臨界擺幅(Subthreshold swing, SS)、以及電流斷通比(On/off current ratio)之關係為模擬重點。藉由三維模擬結果深入探討FinFET元件電特性之行為以及其在抑制短通道效應(Short channel effect, SCE)之機制，以作為最佳結構設計與相關製程技術之建立。本論文除完成37-nm 至 18-nm FinFET之模擬及特性分析外，並提出一可有效降低短通道效應之最佳化FinFET設計。

　　As the feature size of VLSI is scaling down, the influence of gate electrode on channel conductivity decreases significantly. In addition, the punch-through effect becomes much serious, which strongly degrades the device performance. To overcome such problems, the use of FinFET, which is with a free-stand three-direction channel, has been shown being able to enhance the function of gate on channel conductivity control and release the punch-through effect. However, the partial inducing capability of cannel causes the sensitivity of electrical characteristics. Thus, the FinFET dimensions must be designed for higher on-stat current and lower off-leakage current.
　　The three-dimensional (3D) simulation of FinFET are presented and discussed in this thesis. Electrical characteristics of deep submicron FinFETs including threshold voltage saturation (VTsat), drain induced barrier lowing (DIBL), subthreshold swing (SS), and on/off current ratio are analyzed in detail. Special emphasis is focused on the optimization of device design and the impact of short channel effects (SCEs) in FinFETs.

References
[1] R. Stratton, “Diffusion of hot and cold electrons in semiconductor barriers,” Phys. Rev., vol. 126, no. 6, pp. 2002–2014, 1962.
[2] P.-K. Bondyopadhyay, “Moore’s Law Governs the Silicon Revolution”, Proc. IEEE, vol. 86, no. 1, pp. 78–81, 1998.
[3] International Technology Roadmap for Semiconductors (ITRS) : 2002 Update, http://public.itrs.net/
[4] D. Hisamoto, W.-C. Lee, J. Kedzlerski, E. Anderson, H. Takeuchi, K. Asano, T.-J. King, J. Boker, and C. Ha, “A Folded-channel MOSFET for Deep-sub-tenth Micron Era,” in Proc. IEDM, pp. 1032–1034, 1998.
[5] D. Hisamoto, T. Kachi, S. Tsujikawa, A. Miyauchi, K. Kusukawa, N. Sakuma, Y. Homma, N. Yokoyama, F. Ootsuka, and T. Ona, “A Compact FD-SOI MOSFETs Fabrication Process Featuring SixGe1-x Gate and Damascene-Dummy SAC,” in Symp. VLSI Technol. Dig. Tech. Papers, pp. 208–209, 2000.
[6] R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, “30 nm Physical Gate Length CMOS Transistors with 1.0 ps n-MOS and 1.7 ps p-MOS Gate Delays,” in Proc. IEEE IEDM, pp. 45–48, 2000.
[7] R. Chau, J. Kavalieros, B. Doyle, A. Murthy, N. Paulsen, D. Lionberger, D. Barlage, R. Arghavani, B. Roberds, and M. Doczy, “A 50 nm Depleted-Substrate CMOS Transistor (DST),” in Proc. IEDM, pp. 29.1.1–29.1.4, 2001.
[8] Z. Krivokapic,W. Maszara, F. Arasnia, E. Paton, Y. Kim, L. Washington, E. Zhao, J. Chan, J. Zhang, A. Marathe, and M.-R. Lin, “High Performance 25 nm FDSOI Devices with Extremely Thin Silicon Channel,” in IEEE Symp. VLSI Technol. Dig. Tech. Papers, pp. 131–132, 2003.
[9] Meikei Ieong, H-S Philip Wong, Edward Nowak, Jakub Kedzierski, Erin C. Jones, “High Performance Double-Gate Device Technology Challenges and Opportunities” in Proc. ISQED, 2002.
[10] B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau, “Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout,” in IEEE Symp. VLSI Technol. Dig. Tech. Papers, pp. 133–134, 2003.
[11] M. Ieong, B. Doris, J. Kedzierski, K. Rim, M. Yang, and W. Haensch, “Ultra Small SOI MOSFETs,” in Proc. IEEE Nanoelectronics Workshop, pp. 2–3, 2003.
[12] F.-L. Yang, H.-Y. Chen, F.-C. Chen, Y.-L. Chan, K.-N. Yang, C.-J. Chen, H.-J. Tao, Y.-K. Choi, M.-S. Liang, and C. Hu, “35 nm CMOS FinFETs,” in IEEE Symp. VLSI Technol. Dig. Tech. Papers, 2002.
[13] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub 50-nm FinFET," in IEDM Tech. Digest, pp. 67–70, 1999.
[14] D. M. Fried, A. P. Johnson, E. J. Nowak, J. Rankin, and C. R. Willets, "A sub-40 nm Body-Thickness N-type FinFET," Conference Digest, 59th Device Research Conference, pp. 24-25, June, 2001.
[15] J. Kedzierski, D. M. Fried, E. J. Nowak, T. Kanarsky, J. Rankin, H. Hanafi, W. Natzle, D. Boyd, Y. Zhang, R. Roy, J. Newbury, C. Yu, Q. Yang, P. Saunders, C. Willets, A. Johnson, S. Cole, H. Young, N. Carpenter, D. Rakowski, B. A. Rainey, P. Cottrell, M. Ieong, and P. Wong, “High-Performance Symmetric Gate and CMOS-Compatible Vt Asymmetric Gate FinFET Devices,” IEDM Tech. Digest, pp. 437–440, 2001.
[16] Y. Taur, “Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs,” IEEE Trans. Electron Devices, vol.48, no.12, pp. 2861–2869, Dec., 2001.
[17] DEVISE, Release 9.5, ISE AG, Zurich, 2004.
[18] DESSIS, Release 9.5, ISE AG, Zurich, 2004.
[19] J. D. Bude, “MOSFET modeling into the ballistic regime,” in Int. Conf. Simulation of Semiconductor Processes and Devices (SISPAD), pp. 23–26, 2000.
[20] K. Bløtekjær, “Transport equations for electrons in two-valley semiconductors,” IEEE Trans. on Electron Devices, vol. ED-17, no. 1, pp. 38–47, 1970.
[21] A. Benvenuti, M. R. Pinto, J. W. M. Coughran, N. L. Schryer, C. U. Naldi, and G. Ghione, “Evaluation of the influence of convective energy in HBTs using a fully hydrodynamic model,” in IEDM Tech. Digest, pp. 499–502, 1991.
[22] S. Szeto and R. Reif, “A unified electrothermal hot-carrier transport model for silicon bipolar transistor simulation,” Solid State Electronics, vol. 32, no. 4, pp. 307–315, 1989.
[23] A. Pierantoni, A. Liuzzo, P. Ciampolini, and G. Baccarani, “Three-dimensional implementation of a unified transport model,” in SISDEP, pp. 125–128, 1993.
[24] D. Chen, Z. Yu, K.-C. Wu, R. Goosens, and R. W. Dutton, “Dual energy transport model with coupled lattice and carrier temperatures,” in SISDEP-5, Vienna, pp. 157–160, Sept., 1993.
[25] Y. Apanovich, E. Lyumkis, B. Polsky, A. Shur, and P. Blakey, “Steady-state and transient analysis of submicron devices using energy balance and simplified hydrodynamic models,” IEEE Transactions on CAD, vol. 13, pp. 702–710, June, 1994.
[26] B. Baccarani and M. R. Wordeman, “An investigation of steady-state velocity overshoot in Silicon,” Solid State Electronics, vol. 28, no. 4, pp. 407–416, 1985.
[27] D. Chen, E. Sangiori, M. R. Pinto, E. C. Kan, U. Ravaioli, and R. W. Dutton, “An improved energy transport model including nonparabolicity and non-Maxwellian distribution effects,” IEEE Transactions on Electron Devices, vol. ED-39, pp. 26–28, January, 1992.
[28] M. G. Ancona and H. F. Tiersten, “Macroscopic physics of the silicon inversion layer,” Phys. Rev. B, vol. 35, no. 15, pp. 7959–7965, May, 1987.
[29] M. G. Ancona and G. J. Iafrate, “Quantum correction to the equation of state of an electron gas in a semiconductor,” Phys. Rev B, vol. 39, no. 13, pp. 9536–9540, May, 1989.
[30] A. Wettstein, “Quantum effects in MOS devices,” Ph.D. thesis, ETH Zürich, 2000.
[31] C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, “A Physically Based Mobility Model for Numerical Simulation of Nonplanar Devices,” IEEE Trans. on CAD, vol. 7, no. 11, pp. 1164–1171, 1988.
[32] M. N. Darwish, J. L. Lentz, M. R. Pinto, P. M. Zeitzoff, T. J. Krutsick, and H. H. Vuong, “An Improved Electron and Hole Mobility Model for General Purpose Device Simulation,” IEEE Trans. Electron Devices, vol. 44, no. 9, pp. 1529–1538, 1997.
[33] C. Canali, G. Majni, R. Minder, and G. Ottaviani, “Electron and hole drift velocity measurements in Silicon and their empirical relation to electric field and temperature,” IEEE Trans. on Electron Devices, vol. ED-22, pp. 1045–1047, 1975.
[34] D. M. Caughey and R. E. Thomas, “Carrier mobilities in Silicon empirically related to doping and field,” Proc. IEEE, pp. 2192–2193, Dec. 1967.
[35] L. Huldt, N. G. Nilsson, and K. G. Svantesson, “The temperature dependence of band-to-band Auger recombination in silicon,” Appl. Phys. Letters, vol. 35, no. 10, pp. 776, 1979.
[36] W. Lochmann and A. Haug, “Phonon-assisted Auger recombination in Si with direct calculation of the overlap integrals,” Solid State Communications, vol. 35, pp. 553–556, 1980.
[37] R. Häcker and A. Hangleiter, “Intrinsic upper limits of the carrier lifetime in silicon,” Journal of Applied Physics, vol. 75, pp. 7570–7572, 1994.