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研究生: 王仁柏
Wang, Jen-Po
論文名稱: 利用感應耦合式電漿蝕刻系統研製閘極掘入氮化鋁鎵/氮化鎵高速電子遷移率電晶體
Recessed Gate AlGaN/GaN High Elctron Mobility Transistors Using Inductively Coupled Plasma Etching
指導教授: 方炎坤
Fang, Yean-Kuen
王永和
Wang, Yeong-Her
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2013
畢業學年度: 101
語文別: 英文
論文頁數: 46
中文關鍵詞: 氮化鎵氮化鋁鎵閘極掘入感應耦合式電漿蝕刻
外文關鍵詞: AlGaN, GaN, gate recess, inductively coupled plasma etch
相關次數: 點閱:96下載:19
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  • 本論文利用感應耦合式電漿蝕刻系統進行乾式蝕刻從而完成閘極掘入之製程。閘極掘入的目的是為了藉由調控閘極金屬與通道間之距離,增加閘極對通道的控制能力,降低元件臨界電壓。為了完成閘極掘入,本論文分析了各項主要製程參數對蝕刻效果的影響。由結果可以知道蝕刻功率對蝕刻速率有相當大的影響。
    我們成功利用感應耦合式電漿蝕刻系統完成了閘極掘入深度為14nm的閘極掘入氮化鋁鎵/氮化鎵高速電子遷移率電晶體。傳統高速電子遷移率電晶體的最大轉導和臨界電壓分別為88mS/mm和-4.2V,而閘極掘入高速電子遷移率電晶體的最大轉導和臨界電壓分別為115mS/mm和-1.33V。

    The use of inductively coupled plasma etcher system to GaN gate recess process is demonstrated. Gate recess modulates the distance between the gate metal and the two-dimensional electron gas. The threshold voltage and related device performance can be adjusted. In order to accomplish the gate recess process, etching parameters and behavior of the inductively coupled plasma etcher system is investigated. It can be found out that the etch rates were strongly influenced by ICP power.
    The recessed gate AlGaN/GaN high electron mobility transistors with a recess depth of 14nm have been successfully fabricated. For the conventional AlGaN/GaN HEMTs, the transconductance and the threshold voltage were 88 mS/mm and – 4.2 V. For the recessed-gate AlGaN/GaN HEMTs, the transconductance and the threshold voltage were 115 mS/mm and – 1.33 V.

    Contents Abstract II Contents III List of Tables VI List of Figures VII Introduction 1 1.1 Background 1 1.2 Motivation 3 1.3 Organization 4 Experiments 5 2.1 AlGaN/GaN Heterostructure 5 2.2 Gate Recess 7 2.2.1 Drain source current 7 2.2.2 Transconductance 8 2.2.3 Threshold voltage 8 2.3 Inductively Coupled Plasma Etcher 9 2.3.1 Introduction 9 2.3.2 System structure 10 2.3.3 Etching mechanism 10 2.4 Device Fabrication Procedures 11 2.4.1 Mesa Isolation 11 2.4.2 Ohmic Contact Technique 12 2.4.3 Gate Recess 13 2.4.4 Gate Formation 13 Result and Discussion 15 3.1 Etch Rate with parameters 15 3.1.1 Effect of ICP power on etch rate 15 3.2.2 Effect of chamber pressure on etch rate 16 3.2.3 Effect of gas flow rate on etch rate 17 3.2 DC Characteristic 18 3.2.1 The saturated drain current 18 3.2.2 The transconductance 18 3.2.3 The breakdown voltage and gate leakage current 20 3.3 Summary 20 Conclusion and Future Work 22 4.1 Conclusion 22 4.2 Future Work 22 References 42

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