自1964年摩爾定律提出以來，半導體發展技術一直不斷地推進，元件尺寸不斷的微縮，以滿足市場需求。隨著元件尺寸縮小，半導體產業也面臨諸多挑戰。在元件微縮過程，傳統平面式電晶體因受到短通道效應的限制，發展出鰭式電晶體。然而，當通道尺寸縮小至 5 奈米節點時，鰭式電晶體仍難以有效抑制短通道效應，因此進一步發展出環繞式閘極電晶體。由於環繞式閘極電晶體採用閘極完全包覆通道的結構，不僅提升了閘極控制能力，還優化了電晶體特性。不過奈米片電晶體的結構雖然加強閘極控制能力，卻也導致電場增強，使閘極引致汲極漏電流增加，進而提升功耗。
本論文主要為利用Sentaurus TCAD建構並模擬符合IRDS提供的奈米片電晶體，探討閘極引致汲極漏電流，比較三種不同材料下的內、外側壁絕緣層之間的特性差異，並找出最佳材料組合後。接著，進一步分析側壁絕緣層的長度與元件摻雜深度對於漏電流之影響，透過這些研究，期許能夠降低漏電流，進而減少元件的功耗。

Since the introduction of Moore’s Law in 1964, semiconductor technology has continuously advanced, with device dimensions steadily shrinking to meet market demands. As device scaling progresses, the semiconductor industry faces numerous challenges. Due to the limitations imposed by short-channel effects, traditional planar transistors evolved into FinFETs. However, when the channel dimensions shrink to the 5 nm node, FinFETs struggle to effectively suppress short-channel effects, leading to the development of gate-all-around (GAA) MOSFETs. GAA MOSFET enhances gate control capability and improves transistor performance by fully surrounding the channel with the gate. Nevertheless, while the nanosheet transistor structure strengthens gate control, it also intensifies the electric field, increasing gate-induced drain leakage (GIDL) and consequently raising power consumption.
This study utilizes Sentaurus TCAD to construct and simulate nanosheet transistors following the IRDS roadmap, focusing on the investigation of gate-induced drain leakage. It compares the characteristics of inner and outer spacer dielectric layers composed of three different materials to determine the optimal material combination. Subsequently, the study further examines the impact of spacer length and doping depth on leakage current. Through these investigations, the research aims to reduce leakage current and, in turn, lower overall power consumption.

[1] Moore, Gordon E. "Cramming More Components onto Integrated Circuits, Reprinted from Electronics, Volume 38, Number 8, April 19, 1965, Pp. 114 Ff." IEEE solid-state circuits society newsletter, vol. 11, no. 3, 2006, pp. 33-35.
[2] Khanna, Vinod Kumar, and Vinod Kumar Khanna. "Short-channel effects in MOSFETs." Integrated Nanoelectronics: Nanoscale CMOS, Post-CMOS and Allied Nanotechnologies (2016): 73-93.
[3] Maniyar, Ashraf, et al. "Impact of process-induced inclined sidewalls on gate-induced drain leakage (GIDL) current of nanowire GAA MOSFETs." IEEE Transactions on Electron Devices 69.9 (2022): 4815-4820.
[4] Manchala, Venkat Subba Rao, and G. Ramana Murthy. "Low-Power and Low-Leakage Design Techniques in CMOS Technology." 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI). IEEE, 2021.
[5] Fan, Jiewen, et al. "Insight into Gate-Induced Drain Leakage in Silicon Nanowire Transistors." IEEE Transactions on Electron Devices 62.1 (2014): 213-19.
[6] Sreenivasulu, V Bharath and Vadthiya Narendar. "Design Insights of Nanosheet Fet and Cmos Circuit Applications at 5-Nm Technology Node." IEEE Transactions on Electron Devices, vol. 69, no. 8, 2022, pp. 4115-22.
[7] Jurczak, Malgorzata et al. "Review of Finfet Technology." 2009 IEEE international SOI conference, IEEE, 2009, pp. 1-4.
[8] Mari, Lorenzo. "A Comparison of FinFET Configurations." EE Power, 2020, https://eepower.com/technical-articles/a-comparison-of-finfet-configurations/. Accessed 20 Feb. 2025.
[9] Ajayan, J et al. "Nanosheet Field Effect Transistors-a Next Generation Device to Keep Moore's Law Alive: An Intensive Study." Microelectronics Journal, vol. 114, 2021, p. 105141.
[10] Synopsys. "TCAD Technology for Process and Device Simulation." Synopsys, https://www.synopsys.com/manufacturing/tcad.html. Accessed 20 Feb. 2025.
[11] Synopsys, "SentaurusTM Device User Guide," Version T-2022.03, March 2022.
[12] Roy, Kauschick, Saibal Mukhopadhyay, and Hamid Mahmoodi-Meimand. "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer Cmos Circuits." Proceedings of the IEEE 91.2 (2003): 305-27.
[13] Chauhan, Yogesh Singh et al. Finfet Modeling for Ic Simulation and Design: Using the Bsim-Cmg Standard. Academic Press, 2015.
[14] Fan, Jiewen, et al. "Insight into Gate-Induced Drain Leakage in Silicon Nanowire Transistors." IEEE Transactions on Electron Devices 62.1 (2014): 213-19.
[15] Dabhi, Chetan Kumar et al. "Compact Modeling of Temperature-Dependent Gate-Induced Drain Leakage Including Low-Field Effects." IEEE Transactions on Electron Devices, vol. 66, no. 7, 2019, pp. 2892-97.
[16] "International Roadmap for Devices and Systems (IRDS™) 2018 Edition." https://irds.ieee.org/editions/2018/more-moore (accessed June 11, 2024).
[17] Wong, Hiu-Yung, et al. "Modified Hurkx Band-to-Band-Tunneling Model for Accurate and Robust Tcad Simulations." Microelectronics Reliability, vol. 104, 2020, p. 113552.
[18] Nandi, Ashutosh et al. "Design and Analysis of Analog Performance of Dual-K Spacer Underlap N/P-Finfet at 12 Nm Gate Length." IEEE Transactions on Electron Devices, vol. 60, no. 5, 2013, pp. 1529-35.
[19] Pal, Pankaj Kumar et al. "Investigation of Symmetric Dual-K Spacer Trigate Finfets from Delay Perspective." IEEE Transactions on Electron Devices, vol. 61, no. 11, 2014, pp. 3579-85.
[20] Panigrahy, Asisa Kumar et al. "Spacer Dielectric Analysis of Multi-Channel Nanosheet Fet for Nanoscale Applications." IEEE Access, 2024.
[21] Huang, Ya-Chi et al. "Speed Optimization of Vertically Stacked Gate-All-around Mosfets with Inner Spacers for Low Power and Ultra-Low Power Applications." 20th International Symposium on Quality Electronic Design (ISQED), IEEE, 2019, pp. 231-34.