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研究生: 林敬惟
Lin, Jing-Wei
論文名稱: 電流考量之電源與接地線類比積體電路繞線器
Current-Driven Power/Ground Router for Analog ICs
指導教授: 何宗易
Ho, Tsung-Yi
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 英文
論文頁數: 43
中文關鍵詞: 電遷移電源與接地線史坦納樹繞線器電壓降類比
外文關鍵詞: Electromigration, Power/Ground, Steiner tree, Router, IR-drop, Analog
相關次數: 點閱:97下載:2
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  • 相對於應用在數位積體電路上的電源與接地線繞線,類比積體電路上面的研究仍尚未成熟。傳統的類比電路電源與接地線繞線是使用人工的方式並且採用貪婪策略來進行繞線。然而,隨著類比積體電路設計規模越來越大,導致設計者在繞線過程中需要花費更多的時間,並使得以往所採取的貪婪策略變得十分沒有效率。此外,由於導線寬度的不足,過量的電流密度將導致類比電路上導線的電子漂移現象,而產生斷路和短路的情況,這將可能導致晶片的永久性故障。而導線過細,導致電阻上升的情況,將產生嚴重的電壓降情形,將導致類比電路的供電不足而促使性能下降,甚至導致功能錯誤。因此,在繞現階段必須考慮電流密度和導線電阻。在本篇論文中提出了一種自動化類比電路上的電源與接地線繞線器,並且同時考量電子漂移與電壓降的情況。在全面繞線階段,我們將電流考量避免電子漂移的直線史坦納樹問題,轉換成運輸問題,並計算出一個最佳解的最小線路面積繞線結果。根據最佳結果,我們將電線合併,用以提高可繞度及減輕擠塞情況。這個電線合併的步驟將釋放更多的可繞線區域;將提供更大的繞線區域,使我們在之後為了減少電壓降而採取的線寬拓展方式中,得到幫助。最後,在細部繞線步驟,我們求得一個可行的繞線解,之後使用線寬拓展方法來減少電壓降的情況。實驗結果證明的我們提出的方法可快速且有效率的求得繞線結果。

    Compared with the Power/Ground (P/G) routing in digital ICs, the P/G routing in analog ICs has not yet been well researched. Traditional P/G routing in analog ICs adopts greedy strategies to route nets by analog designers. However, the growing scale of analog ICs leads human designers to cause a lot of time in the routing procedure and makes the greedy strategies ineffective. Furthermore, due to insufficient wire widths, the critical excessive current densities in analog ICs can cause a wire open and short (voids and hillocks) by electromigration. It may lead to the permanent failure of a circuit. And the finite resistance has detrimental impacts in the form of IR-drop; it would cause the analog ICs with insufficient power supply to decrease the performance or even lead the functional errors. Therefore, it is desirable to consider current densities and wire resistance in the routing stage. In this paper, an automatic analog P/G router considering electromigration and IR-drop is proposed. In the global routing stage, we model current-driven electromigration-aware rectilinear Steiner tree (CDEARST) problem as a transportation formulation and obtain an optimal solution with the minimum wire area. Based on the optimal solution, we bundle the wires to enhance the routability and alleviate congestions. The bundling step would free more routable areas; it helped us to expand the wire width for resistance decreasing and IR-drop reducing. Finally, in the detailed routing step, we obtain a routing solution and then wire width extension method is adopted to reduce IR-drop. Experimental results prove the effectiveness and efficiency of our algorithm.

    Chinese Abstract . . . .. . . . . . . . . . . . . . .i Abstract . . . . . . . . . . . . . . . . . . . . . iii List of Tables . . . . . . . . . . . . . . . . . . vii List of Figures . . . . . . . . . . . . . . . . . viii Chapter 1. Introduction . . . . .. . . . . . . . . . 1 1.1 Previous Work . . . . . . . . . . . . . . . . 4 1.2 Our ontribution . . . . . . . . . . . . . . . 6 Chapter 2. Problem Formulation . . . . . . . . . . . 8 Chapter 3. Property . . . . . . . . . . . . . . . . 11 Chapter 4. Algorithm . . . . . . . . . . . . . . . .15 4.1 Obstacle-Avoiding Wirelength Calculation . . 15 4.1.1 Obstacle-Avoiding Spanning Graph (OASG) . 17 4.1.2 Obstacle-Avoiding Shortest Path (OASP) . .17 4.2 Transportation Problem Approach . . . . . . . 18 4.2.1 Basic Feasible Solutions . . . . . . . . .19 4.2.2 Optimality Test . . . . . . . . . . . . . 21 4.2.3 Wire Size Constraint Model. . . . . . . . 26 4.3 Routing and IR-drop Reduction . . . . . . . . 27 4.3.1 Routing . . . . . . . . . . . . . . . . . 28 4.3.2 IR-drop Reduction . . . . . . . . . . . . 30 4.4 Complexity . . . . . . . . . . . . . . . . . 31 Chapter 5. Experimental Results. . . . . . . . . . 34 Chapter 6. Conclusion . . . . . . . . . . . . . . . 41 Bibliography . . . . . . . . . . . . . . . . . . . .42

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