三維封裝技術是目前被認定為是超越摩爾定律，持續實現電子封裝結構小型化、高密度以及多功能化的解決方案。三維封裝是一種利用堆疊的方式將各個不同功能的元件整合在一起，而其中矽穿孔技術為三維封裝電路中之垂直通道，此技術能夠縮短彼此間之傳輸距離，也能提供內部電導通，以及熱導通的功能。然而當尺寸逐漸縮小時，因TSV結構中，材料間熱膨脹係數不匹配的效應，造成在外加溫度負載下，所產生的散熱問題與熱應力集中的現象，導致元件失效，仍是目前所需克服的問題。
TSV結構製程技術主要分為導孔形成、導孔填充、晶圓薄化以及晶圓接合四大製程。本文之研究以探討在即將晶圓薄化前，矽穿孔之盲孔結構之熱分析以及電性分析;由於TSV結構的關係，導致在溫度負載下造成的熱應力集中問題，進而發生失效或破壞。透過實驗的方式並搭配實驗室裡的奈米壓痕專用超高精度樣品環境控制腔體，即時擷取材料受熱的影響及產生的行為，並找出元件產生破壞的原因。
本實驗之矽穿孔結構，製作方式以感應式耦合蝕刻來製作導孔、高密度電漿化學氣相沉積沉積二氧化矽，以及雙電子槍蒸鍍機填入鈦以及銅膜，利用研磨拋光機去除表面銅膜，利用直流量測系統量測電容-電壓曲線，配合掃描式電子顯微鏡來找出二氧化矽之介電層厚度。
熱破壞實驗-時間相依介電層崩潰分別對經觀察以及換算後之二氧化矽介電層厚度，分別為152nm,400nm以及860nm來做測試，發現當溫度越高時其崩潰時間(TBD)較早發生，且崩潰時間將隨著厚度的增加而增。其主要原因來自於，當介電層厚度越厚，所受熱影響的電載子較不容易因穿隧行為而使介電層發生失效，而當金屬層受到高溫而冷卻到室溫時，因其晶粒成長，使得晶粒與晶粒間的縫隙減少，導致金屬層與矽之間產生脫層的現象。而在矽穿孔結構角落部分，受到因受熱應力的影響，使得薄膜與薄膜間產生裂痕，金屬層有機會經擴散的方式進入介電層破壞整體的結構電性。

Recently, through silicon via structure (TSV) technology has become important in three-dimension technology, because it provides the short distance connection can also be internal electrical conduction and thermal conduction. TSV structure of process technology divided into via forming, via filling, wafer thinning and wafer bounding .
This study focus on the modeling establishment for evaluation of the thermal failure arising at the Cu constrained in a blind through silicon via (TSV) structure before wafer thinning. Due to coefficient of thermal expansion mismatch between the materials, leading to thermal-mechanical stress accumulation problems by thermal load, and thus cause failure or damage. Use experiment of the thermal test- Time Dependent Dielectric Breakdown (TDDB) to observe current change with time, for 152nm、400nm and 860nm dielectric layer thickness, respectively .

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