本論文中，我們主要研究P型金氧半場效電晶體之負偏壓溫度不穩定性可靠度分析以及閘極接地N型金氧半場效電晶體靜電防護元件之靜電放電現象。藉由直接基板電壓量測，我們探討閘極接地N型金氧半場效電晶體靜電防護元件在不同電流下的動態電流分佈。
第二章探討先進製程之P型金氧半場效電晶體的負偏壓溫度不穩定性可靠度分析。我們證明出氧化層缺陷以及接面缺陷皆會導致P型金氧半場效電晶體之臨界電壓漂移，尤其是當尺寸縮小到奈米級。此外，核心元件的遷移率退化較輸出輸入元件為更嚴重。根據我們的汲極飽和電流退化模型，操作電壓對汲極飽和電流退化之影響可以被預測到。再者，藉由比較不同通道方向之超薄氧化層元件之可靠度，得知通道方向<100>之元件是個具有較高遷移率且能維持相同可靠度之元件。
第三章裡，我們研究閘極接地N型金氧半場效電晶體靜電防護元件之基極電壓沿著通道傳輸之情形。這研究描述出如何耦合電壓到基板以及如何藉由基板做傳輸動作。藉由傳輸線的理論，此互相傳輸之行為能被闡釋。再者，我們研究在傳輸線脈波事件下元件之電流分佈情形。最後，自我一致效應，即在傳輸線脈波事件下整個元件之動態基極分佈情形，也被提出。
第四章裡，我們研究閘極接地N型金氧半場效電晶體靜電防護元件在寄生雙極性電晶體開啟時所需之基極電壓。首先，最小能使得寄生雙極性電晶體開啟並且維持之基極電壓至少是0.9伏特，這值大於先前文獻所提到的值。再者，基極電壓會隨電流的增加而增加，這也不同於先前文獻所提出之基極電壓與電流無關的情形。最後，我們藉由模擬結果可以發現到導致在直流與脈波量測下基極電壓不一致之機制。
第五章裡，我們探討不同的汲極設計對靜電防護表現之影響。由於反轉溫度隨摻雜濃度的增加而增加，所以一個有輕摻雜汲極區之N型金氧半場效電晶體將會有著兩種不同的反轉溫度。根據這個觀念，闡述製程結合佈局如何影響元件靜電放電表現之理論被首次提出。
在最後的第六章裡，摘要幾個關鍵結果，並對此論文的未來方向做一建議。

In this dissertation, we investigate the negative bias temperature instability (NBTI) of advanced PMOS transistors and the electrostatic discharge (ESD) phenomenon of the grounded gate NMOS (GGNMOS). By directly measuring the substrate potential, we explore the dynamic current distribution of GGNMOS devices under various levels of high current stress.
NBTI of state-of-the-art PMOS transistors is investigated in Chapter 2. It is demonstrated that both oxide traps and interface traps can induce a significant shift in the threshold voltage of PMOSFETs, particularly as we continue to scale into the nanometer regime. Furthermore, we demonstrate that the mobility degradation of core devices is more serious than that of I/O devices. According to the Idsat degradation model, the impact of Vdd on Idsat degradation under a fixed amount of NBTI-induced damage is predicted. Moreover, through comparing the reliability of PMOSFETs with different channel orientations, it is shown that devices with <100> channel direction is a superior one with higher fresh mobility while maintaining the same degradation.
In Chapter 3, the substrate potential propagation along the channel direction of GGNMOS devices is presented and investigated. The study presents how to couple the voltage to the P-substrate and how to propagate through the substrate. This mutual-propagation phenomenon can be explained by the transmission-line theorem. Furthermore, the time evolution of the current distribution for a device under a Transmission Line Pulse (TLP) stress event is discussed. Finally, the self-consistent effect, which illustrates the dynamic base region across the device under the TLP stress, is also addressed.
In Chapter 4, the substrate potential needed to trigger a GGNMOS into the snapback region under TLP stress is investigated. Firstly, we show that the minimum substrate potential to turn on and sustain the parasitic n-p-n bipolar is at least 0.9 V, which is larger than the values previously published in literature. Secondly, we find the substrate potential increases with the drain current, which also differs from the previously reported independence of the substrate potential on the stress level. Lastly, the mechanism behind the substrate potential inconsistency between DC and pulse measurement is explained in detail through simulation results.
In Chapter 5, the influence of drain engineering on the device ESD performance is studied. Since the turnover temperature (TOT) increases with the doping concentration, an NMOSFET will inherit two different TOTs. Based on this, a new theory combining the process flow and layout is derived to explain how the two factors affect the device ESD performance.
In Chapter 6, we summarize key findings and suggest the direction of future work for this study.

Chapter 1
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Chapter 2
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Chapter 3
[3.1] A. Amerasekera, S. Ramaswamy, M. C. Chang and C. Duvvury, “Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations,” in Proc. Int. Reliab. Phys. Symp., pp. 318-326, 1996.
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[3.4] T. Toyabe, K. Yamaguchi, S. Asai, and M. Mock, “A numerical model of avalanche breakdown in MOSFETs,” IEEE Trans. Electron Devices, vol. 25, pp. 825-832, Jul. 1978.
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Chapter 4
[4.1] A. Amerasekera, S. Ramaswamy, M.-C. Chang, and C. Duvvury, “Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations,” in Proc. Int. Reliab. Phys. Symp., pp. 318-326, 1996.
[4.2] S. Ramaswamy, A. Amerasekera, and M.C. Chang, “A Unified Substrate Current Model for Weak and Strong Impact Ionization in sub-0.25μm NMOS Devices,” in IEDM Tech. Dig., pp. 885-888, 1997.
[4.3] T. Skotnicki, G. Merckel, and A. Merrachi, “New Physical Model of Multiplication-Induced Breakdown in MOSFETs,” Solid-State Electron., vol. 34, pp. 1297-1307, Nov. 1991.
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Chapter 5
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