本論文設計研究45-90 GHz寬頻倍頻器及寬頻V-band對數功率偵測器毫米波晶片、及具60-GHz CMOS都卜勒雷達感測晶片系統之實驗量測。論文第一部分為使用馬遜平衡器之45-90 GHz寬頻倍頻器，採用single-balanced架構，利用輸入端的馬遜平衡器，使得兩顆MOS的基頻項在輸出端有180度的相位差而互相抵銷，因此可省去基頻的濾波電路，並達到晶片面積微小化的目的。論文第二部分為V-band寬頻對數功率偵測器毫米波晶片，主體架構採用連續偵測對數放大器架構，增益級則採用四級疊接組態毫米波寬頻放大器，替換掉傳統限制放大器設計方式，而整體電路特性有寬動態範圍、低對數錯誤與寬頻表現。對數功率偵測器整合在系統電路中，可使其應用於內建測試機制、自動功率控制等。晶片皆採用TSMC CMOS 90-nm GUTM製，電路設計使用Agilent ADS與3-D全波電磁模擬軟體進行模擬，晶片量測採fully on-wafer方式進行量測。論文第三部分為具自動化洩漏迴波消除功能之60-GHz CMOS都卜勒雷達人體呼吸心跳訊號感測晶片系統之實驗量測, 介紹了都卜勒雷達感測晶片之量測原理與電路設計考量，並且實際進行實驗人體呼吸心跳訊號量測。

This thesis presents the design of CMOS millimeter-wave (MMW) frequency doubler and power detector, implemented by standard TSMC 90-nm GUTM CMOS process, and the experimental measurement of a 60-GHz CMOS vital-signs Doppler radar (VSDR) RF sensor with automatic clutter cancellation (ACC). In a 45–90 GHz CMOS frequency doubler, the single-balanced topology with marchand balun is adopted. For bandwidth enhancement, an input marchand balun with improved topology is designed. In the design of a V-band CMOS logarithmic power detector, the modified successive detection logarithmic amplifier (SDLA) structure is proposed. Instead of using traditional differential limiting amplifiers, the MMW amplifiers are applied for the gain cells (to the V-band). Furthermore, by adopting the inter-stage matching skills, a wideband gain cell is designed to enhance the bandwidth performance of power detector. In the final part, extensive experimental measurement of 60-GHz vital-signs Doppler radar (VSDR) RF sensor with automatic clutter cancellation (ACC) is presented. The tiny actuator vibration and the human vital signs are successfully detected. The heartbeat measurement results are well agreed with BIOPEC ECG.

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