在追隨摩爾定律以及製程技術持續進步的情況下，電晶體的尺度及效能不斷提升，然而短通道效應也伴隨尺寸微縮而來。目前半導體工業多使用多閘極結構，如鰭式電晶體或環繞式閘極電晶體，透過增加閘極控制能力來抑制短通道效應。同時，銅金屬導孔的電阻在更先進的技術結點被預期將快速增加，為元件及積體電路效能帶來更多的挑戰。
在這篇論文中，我們運用TCAD中的半導體製程模擬工具建立了七奈米節點的鰭式場效電晶體與其特性；而同一技術節點的銅金屬導孔模型也被建立，並透過導入三維局部電阻率模型對金屬導孔電阻進行仔細評估，在後端製程中，常見的變異量，如臨界尺寸的偏差、對準誤差，亦被納入討論。我們將鰭式電晶體的模型與萃取出的金屬導孔電阻整合，以預測後端製程在七奈米節點對元件電氣特性的影響。
最後，我們使用相同的實驗方法將鰭式電晶體與銅金屬導孔微縮至五奈米節點，比較不同節點間金屬導孔電阻的影響趨勢。我們預期從五奈米節點起，後端製程將對元件特性造成不可忽略的下降。

By following Moore’s Law and the advances of the processing technology, the performances of transistors have been improved rapidly. For the continuous scaling of technology, the short channel effects (SCEs) have surfaced. One of the major solutions is to use 3D structure devices, such as FinFET or Gate-All-Around FET, to overcome SCEs through enhancing the gate controllability. Besides, the resistivity of the Cu vias is believed to increase tremendously at N7. The via resistance brings more challenging issues against the performances of devices and ICs.
In this thesis, we use TCAD tools to construct the FinFET models and to extract device characteristics at N7. The via model at N7 is built and investigated by integrating the 3D local resistivity model into TCAD tools, and the dependence on the CD variations and misalignment are also discussed in depth. We assess the characteristics of FinFET in combination with the extracted via resistances at node 7.
Following the same methodology, the FinFET and the Cu via are scaled toward N5 to compare the impacts of the via resistance from node to node. We conclude that a single via resistance can have substantial impacts on the performances of devices from N5 and beyond.

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