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研究生: 張雅松
Chang, Ya-Sung
論文名稱: 適用於Low-MIPS的多處理器平台的分散式暨嵌入式作業系統的實作
The implementation of the Distributed Embedded Operating System for a Low-MIPS Multiprocessor Platform
指導教授: 楊中平
Young, Chung-Ping
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2007
畢業學年度: 95
語文別: 英文
論文頁數: 151
中文關鍵詞: 即時核心MicroC/OS-II分散式架構嵌入式作業系統
外文關鍵詞: Real-Time Kernel, Distributed Architecture, Embedded OS, MicroC/OS-II
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  • MCS-51族系始於1980年,由Intel所研發出來。由於MCS-51 MCU的功能強大,價格便宜,在工業界廣受歡迎,歷久不衰。直到今日,其所衍生的改良型MCU的種類更是不計其數,這些改良型的MCS-51 MCU具有更高的時脈,更好的電源管理機制,更強大的運算能力。在各行各業的簡單控制的應用上,具有指標的地位。對於比較複雜的應用,單一顆8051或許在運算能力上力有未逮,但是如果我們能夠充分的利用8051相對便宜的優勢,建構出一個使用多顆8051當作核心的運算平台,在性能價格比上將擁有莫大的優勢,因為這樣的平台將相當便宜,而且能夠負擔一定程度的複雜應用。在這篇論文中,我們實做了一個適用於low-MIPS的多處理器平台的分散式暨嵌入式作業系統,平台所使用的作業系統是MicroC/OS-II,一種高效能的即時作業系統。整體系統採用high throughput的架構,每一個8051核心上均運行自己的作業系統,都具有獨立性,核心之間能夠透過溝通機制進行資料的傳遞。為了達到high throughput的目的,我們實做了核心之間的任務轉移(task migration)的機制。使用task migration的機制,我們就能夠實現核心之間的負載平衡(load balancing),這將大大的提高系統整體的效能,更有效率的使用每一個8051核心所擁有的計算能力。同時為了具有擴充性(scalable)跟移植性(portable),我們也實做了高度抽象化的MPI(Message Passing Interface)溝通機制。

    MCS-51 series was first developed in 1980 by Intel. It had become so popular in the industry for its high performance and low cost until now. Nowadays, there are so many kinds of advanced 8051-based MCUs developed, and these advanced 8051-based MCUs have higher frequency, better power consumption management mechanism, and more powerful computing power. It has great influence in all kinds of simple control applications. Single 8051 may has many limitations on complicated applications because of its lower computing power. But we could improve its computing power by building the platform with distributed multi-8051 core. This platform would have such advantages, including low cost and higher performance and would be capable of performing some complicated application. Moreover, this platform could have very good cost/performance ratio.
    In this paper, we propose and implement a distributed embedded operating system for a low-MIPS multiprocessor platform and we use the MicroC/OS-II as our real-time operating system. The whole platform adopts the architecture of high throughput. Every 8051 core is independent and has its own operating system to control all resource it has. All of these cores could pass data through communicating mechanism to one another. For the object of high throughput, we propose the mechanism of task migration among all cores. By task migration, we could achieve the load balancing for our platform. It means that we could improve the performance of our platform by using the computing power of every 8051 core more efficiently. As for the scalability and portability, we propose the mechanism of MPI (Message Passing Interface) with abstraction description.

    CHAPTER 1 INTRODUCTION 14 1.1 INTRODUCTION 14 1.2 HARDWARE/SOFTWARE ARCHITECTURE 15 1.3 MOTIVATION 16 1.4 OVERVIEW OF THIS THESIS 17 1.5 ORGANIZATION OF THIS THESIS 18 CHAPTER 2 RELATED WORKS 20 2.1 REAL-TIME OPERATING SYSTEM 20 2.2 EMBEDDED APPLICATION DESIGNING ISSUES USING A RTOS 22 2.2.1 TIME CONSTRAINTS 23 2.2.2 SAFETY 24 2.2.3 DEVICE DRIVER 25 2.2.4 INTERRUPT SERVICE ROUTINES 25 2.2.5 STORAGE ALLOCATION 25 2.2.6 OPTIMIZING PERFORMANCE 26 2.2.7 DEBUGGING MEMORY PROBLEMS 26 2.3 TASK MIGRATION 27 2.3.1 TASK MIGRATION IN DISTRIBUTED SHARED MEMORY 29 2.3.2 TASK MIGRATION IN GRID ENVIRONMENTS 30 2.3.3 TASK MIGRATION IN VIRTUAL CLUSTER COMPUTER 30 2.3.4 TASK MIGRATION IN MULTI-PROCESSOR SYSTEMS-ON CHIP (MPSOC) 31 2.4 LOAD BALANCING 32 2.5 MESSAGE PASSING 34 2.6 CONFIGURABLE MICROCONTROLLER ARRAY 35 CHAPTER 3 BACKGROUND TECHNOLOGIES 37 3.1 DISTRIBUTED SYSTEM 37 3.1.1 ADVANTAGES OF DISTRIBUTED SYSTEM OVER CENTRALIZED SYSTEMS 38 3.1.2 DISADVANTAGES OF DISTRIBUTED SYSTEMS 40 3.1.3 HARDWARE CONCEPTS 42 3.1.4 SOFTWARE CONCEPTS 45 3.1.5 DESIGNING ISSUES 47 3.1.5.1 Transparency 47 3.1.5.2 Flexibility 50 3.1.5.3 Reliability 52 3.1.5.4 Performance 53 3.1.5.5 Scalability 53 3.2 REAL-TIME KERNEL MICROC/OS-II 54 3.2.1 FEATURES INTRODUCTION 54 3.2.2 MICROC/OS-II KERNEL STRUCTURE 56 3.2.3 MICROC/OS-II TASK STATES 58 3.2.4 REAL-TIME SCHEDULING IN MICROC/OS-II 59 3.3 I2C (INTER-INTEGRATED CIRCUIT) BUS TECHNICAL OVERVIEW 66 3.3.1 THE I2C BUS PROTOCOL 66 3.3.2 I2C BUS ARBITRATION 68 3.3.3 I2C BUS EVENTS 69 3.3.3.1 The START and STOP conditions 70 3.3.3.2 Transmitting a Byte to a Slave 70 3.3.3.3 Receiving a Byte from a Slave 71 3.3.3.4 Getting Acknowledge From a Slave 72 3.3.3.5 Giving Acknowledge to a Slave 73 3.4 MESSAGE PASSING INTERFACE 74 3.4.1 MESSAGE PASSING MODEL 75 3.4.2 MESSAGE PASSING LIBRARY 76 3.4.3 TERMINOLOGIES OF MESSAGE PASSING LIBRARIES 76 3.4.4 PERFORMANCE GUIDELINES 77 CHAPTER 4 IMPLEMENTATIONS 79 4.1 SYSTEM OVERVIEW 79 4.2 HARDWARE PLATFORM AND DEVELOPING ENVIRONMENT 83 4.3 PORTING MICROC/OS-II ON 8051 85 4.4 COMPUTING CPU USAGE 90 4.5 LIGHTWEIGHT I2C DEVICE DRIVER 93 4.5.1 SOFTWARE SIMULATION I2C BUS PROTOCOL 93 4.5.2 OVERCOMING THE PROPAGATION DELAY 96 4.5.3 LIGHTWEIGHT I2C SYNCHRONIZATION 97 4.6 ABSTRACT MESSAGE PASSING LAYER 99 4.7 TASK MIGRATION MECHANISM 105 4.7.1 INTRODUCTION TO TASK MIGRATION 105 4.7.2 DYNAMIC DATA ENCAPSULATION 107 4.7.3 LOAD BALANCING ALGORITHM 109 4.8 TRANSMITTING AND RECEIVING MECHANISMS 113 4.8.1 TRANSMITTING MECHANISM 113 4.8.2 RECEIVING MECHANISM 116 4.9 SUMMARY 118 CHAPTRE 5 EXPERIMENTAL RESULTS 120 5.1 OPERATING SYSTEM OVERHEAD 120 5.2 LIGHTWEIGHT SOFTWARE I2C DATA RATE 123 5.3 EXPERIMENTAL RESULTS 124 5.3.1 SYSTEM THROUGHPUT EVALUATION 125 5.3.2 ALGORITHM COMPARISON 128 5.4 COST/PERFORMANCE RATIO OF OUR SYSTEM 135 5.4.1 COST COMPARISON 136 5.4.2 PERFORMANCE COMPARISON 137 5.4.3 SUMMARY 140 CHAPTER 6 CONCLUSION AND FUTURE WORKS 141 6.1 CONCLUSION 141 6.2 FUTURE WORKS 142 6.3 COMPUTATION SUBTASK MIGRATION IN THE FUTURE WORK 142

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