當金氧半場效電晶體製程技術微縮到深次微米時代時，電晶體元件之電流增益已無法只靠單純的縮小閘極長度。製程技術上的種種限制，如曝光波長的影響、可靠度的考量、抑或是過薄的閘極氧化層導致嚴重的閘極漏電流，增加尺吋向下微縮的困難。
全矽化結構(Fully Silicide)與及應力結構(Strain Technology)為目前在電晶體製程技術上，勢必應用的一種先進製程技術。原因在於其製程技術與現有製程機台相容，且對於元件的效能有一定程度上之提昇。本論文的第二章中，我們利用了閘極上方的接觸蝕刻停止層(Contact Etch Stop Layer, CESL) 及兩種不同的新穎閘極製程技術(Ultimate Spacer Process 及Notch Gate Structure)來對通道產生應力藉以提昇載子的移動力: (1)Ultimate Spacer Process，相較於傳統製程技術，其Spacer形狀有如一個對稱的L形，可以有效率的傳達閘極上方的CESL應力到元件之載子通道。如此更加顯著提升元件應力結構性能; (2) Notch Gate Structure， 為一個新型態之閘極結構，利用橫向過蝕刻閘極的底層，使閘極結內凹。也更容易傳達CESL應力到元件通道。
接著，為了解決薄閘極氧化層所造成之閘極漏電流困擾，因而導入了高介電材料於製程中。但高介電材料卻因其高缺陷特性，使元件的臨界電壓偏高，造成元件製程特性無法達到需要的規格。本論文在第三章節討論如何利用釓摻雜入鉿的薄層裡，藉此調整元件的功函數，使其臨界電壓達到需要的標準。但釓極容易在元件的後續退火過程中，因高溫而產生擴散現象。因此，我們利用氮氣電漿製程去有效的控制釓的摻雜擴散的分佈，藉此去得到較好的臨界電壓控制。此外，我們利用氧氣環境下的後續沉積退火來改善高介電材料的高缺陷性。在不影響元件的等效氧化層(EOT)厚度下，此退火可改善元件的正偏壓溫度不穩定性(PBTI)，時間依靠介電質崩毀(TDDB)及稍微提升元件的載子遷移率。
又在本篇論文的第四章，吾人討論了如何在高介電材料閘極結構下，結合矽鍺通道製程，利用矽鍺材料對矽造成的壓縮應力，提升P型金氧半場效電晶體的特性。
最後，我們考慮高介電材料的未來發展方向。因為傳統金氧半場效電晶體製程都是閘極優先型製程(Gate First)，所以高介電材料非常容易因為後續的高溫源/汲極退火，造成材料品質上的劣化。所以勢必要導入較複雜的閘極後續製程(Gate Last)到高介電材料製程技術裡。因此，我們利用此兩種不同製程的28 奈米金氧半場效電晶體來驗證出閘極後續製程可有效的避免熱預算問題而得到更好之電晶體特性。

As CMOS process scaling down to the deep submicron regime, to enhance device performance with shrinking down gate length becomes very difficult. Many factors such as lithography limitation, large gate leakage and reliability concerns will restrict gate length continuously shrinking. Thus, fully silicide and strain technology have been investigated widely for the advanced CMOS technology, because it is comparable to the present process.
In this dissertation, firstly, we studied how to enhance device performance using two novel gate structures (ultimate spacer process and notch gate structure) to enhance CESL (contact etch stop layer) strain engineering. With the ultimate spacer process, a nice spacer shape will be resulted, and the notch gate features a very narrow bottom structure using over etching. Both of structures can transfer the CESL stress into channel more effectively than the conventional one, thus improving device performance more significantly.
Next, high-k material should be used in deep nano CMOS devices with thinner gate oxide to overcome the increasing gate leakage. But the large traps in the high-k material leads the high-k gate device also has the Fermi-level pinning issue. It would make threshold voltage too high to be optimized. Hence, we incorporated Gd in the Hf-base high-k gate to adjust device work function (chapter 3), and thus shifting the threshold voltage. Besides, we used NH3 plasma treatment to suppress Gd diffusion and thus improving channel interface state, because Gd is very easy to diffuse into Si channel.
For the reliability concern, a post deposition annealing (PDA) under oxygen gas ambient after high-k deposition was used. The PDA process could improve both of the positive bias temperature instability (PBTI) and time dependent dielectric breakdown (TDDB) reliability issues. Moreover, it could also increase device mobility without degrading equivalent oxide thickness (EOT).
Then, in the chapter 4, we describe of merging high-k material and SiGe channel technology to enhance device performance. The SiGe layer on Si substrate provides a compressive stress, which is beneficial to MOSFET.
Finally, we compare the performance of 28 nm high k devices with Gate First and Gate Last approaches, and found that the Gate last process is better for the high-k material is degraded easily in the source/drain annealing process. Thus we conclude the present used Gate first process with a larger thermal budget would be replaced by the Gate last process in future, even although it has more complicated in preparing process.

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