在先進奈米製程下，SRAM 面臨密度小、leakage power 大的問題。因此，Emerging Non-Volatile Memories (NVM) 已經被廣泛討論為傳統SRAM-based Last-Level- Cache (LLC) 的替換品。在NVM 中，Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) 是最被受期待可以取代SRAM 的記憶體。因為STT-MRAM 的read overhead 與SRAM 相近，而且它可以提供更低的leakage power 與更高的密度。但是STT-MRAM 有一個缺點， 就是它write overhead 很 大。為了讓LLC 可以擁有large capacity 與low write overhead 等特點，因此hybrid SRAM/STT-MRAM 的LLC architecture 就被提出，讓LLC 可以擁有STT-MRAM 的大容量的優點與SRAM 的low write overhead 的優點。Hybrid LLC 要表現出它的優點必須依賴Intelligent Block Placement Policy，將write intensive block 擺在SRAM、將read intensive block 擺在STT-MRAM。目前很多研究已經在探討hybrid LLC 的Migration Policy 和Replacement Policy，但是hybrid LLC 的Memory-to-LLC Placement Policy 卻沒有被詳細的探討。在本篇論文中，我們探討Memory-to-LLC Placement Policy ， 它決定每一個從main memory 來的block 應該被擺進hybrid LLC 中的SRAM 或是STT-MRAM。在先前的hybrid LLC work 中， 它們都沒有分析cache 的access behaviors 就直覺性的將block 從main memory 擺進SRAM 或STT-MRAM。這種做法無法發揮hybrid LLC 大容量與low write cost 的優點。此外，我們觀察quad-core processor system 而且4 個CPU 跑4 支不同的benchmark 的access 行為。我們觀察到每一個CPU 的access behavior 會隨著模擬時間有所不同。因此，我們提出Adaptive Memory-to-LLC Placement Policy(AMLP)。AMLP 根據每一個CPU 在不同 的 time phase 的 access behavior 分配 block 到 SRAM 或 STT-MRAM。EPI(energy per instruction) 實驗顯示AMLP 分別在Read-Write Aware Region-Based Hybrid Cache Architecture(RWHCA)、Access-Aware Policies(AAP) 、Adaptive Placement and Migration Policy(APM)、Repetitive Access Aware Placement and Migration(RAP) 中減少分別14.28%, 7.63%, 3.79%, 7.61%。

In modern nano-scale manufacturing, SRAM faces the dual problems of low density, and high leakage power. In light of this, Emerging Non-Volatile Memories (NVM) has been widely discussed as a potential replacement for the traditional SRAM-based Last-Level-Cache (LLC). In NVM, Spin-Transfer Torque Magnetoresistive Random Access Memory(STT-MRAM) is the most anticipated material to replace SRAM, due to the read overhead of STT-MRAM being similar to SRAM, while providing higher density and lower leakage power. However, STT-MRAM has a disadvantage that its write overhead is quite high. So, in order for LLC to have both large capacity and low write overhead, a hybrid SRAM/STTMRAM LLC architecture is proposed, giving LLC the large capacity of STT-MRAM as well as the low write overhead of SRAM. For hybrid LLC to express its advantages, it must rely on Intelligent Block Placement Policy, which places write intensive blocks in SRAM, and read intensive blocks in STT-MRAM. Currently, much research is being done on a Migration Policy and a Replacement Policy of hybrid LLC, but none have investigated on Memory-to-LLC Placement Policy so far. In this thesis, we explore Memory-to-LLC Placement Policy, which decides whether to place blocks from main memory into a hybrid LLC’s SRAM or STT-MRAM. In previous works on hybrid LLC, the access behaviors of cache were not analyzed, and blocks were intuitively placed from main memory into either SRAM or STTMRAM. This method cannot show the advantages in large capacity and low write cost that hybrid LLC has. Additionally, we observe the access behavior of quad-core processors with 4 CPUs running four different benchmarks. We find that each CPU’s access behavior changes depending on simulation time. Therefore, we propose an adaptive memory-to-LLC placement policy (AMLP). AMLP analyzes whether a block should be placed in SRAM or STTMRAM based on each CPU’s access behavior at different time phases. Energy Per Instruction (EPI) experiments show AMLP reduces Read-Write Aware Region-Based Hybrid Cache Architecture(RWHCA), Access-Aware Policies(AAP), Adaptive Placement and Migration Policy(APM), Repetitive Access Aware Placement and Migration(RAP) by 14.28%, 7.63%, 3.79%, and 7.61% respectively.

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