隨著半導體製程的發展，以傳統矽基為主的元件逐漸面臨到物理極限，使晶片的能效難以繼續提升。而鍺基元件因其具有比Si更高的電子和電洞遷移率和較低的摻雜活化溫度以及低功耗的應用，被視為能取代Si的候選材料。儘管如此，Ge依然有諸多材料問題尚待解決，如嚴重的費米能階釘扎及俱生氧化層本身的不穩定性，導致絕緣層/鍺介面容易出現高Dit 的情況，因此限制了Ge基元件的發展。此外，本實驗室通過採用晶片鍵合的方式，製備GeOI晶圓，具備優異的薄膜特性，標示著鍺基元件在低溫下達到優異的電性，已成為可能。
為了配合降低界面缺陷，本研究首先透過臭氧進行介面氧化，隨後採用兩種介面氮化，分別為氨電漿與聯氨，並以使用鰭式電晶體 (FinFET)做為測試元件。在這個過程中，GeOx將轉變為氮氧化鍺(GeON)，大幅提升了漏電情況的惡化。並探討元件在經過氮化處理後，其電性在低溫環境下的趨勢。本實驗所使用的氮化處理方式有兩種 : NH3、N2H4，其中N2H4的氮化方式是用氣體分解的方式進行，有可能導致小尺寸的元件氮化不完全。而NH3則是產生電漿進行表面轟擊，所以在低溫下O3+ NH3的變異性顯得更嚴重

With the continuous advancement of semiconductor technology, conventional silicon-based devices are progressively approaching their fundamental physical limitations. As a result, the improvement of chip energy efficiency has become increasingly constrained, making it difficult to sustain the historical pace of performance gains. In this context, germanium (Ge) has attracted significant attention as a potential alternative channel material to replace silicon (Si). The rationale stems from its intrinsically superior material properties: Ge possesses a substantially higher electron and hole mobility compared with Si, a lower dopant activation temperature that facilitates device fabrication at reduced thermal budgets, and an inherent suitability for low-power applications. These characteristics collectively make Ge a highly attractive candidate for extending CMOS scaling and enabling next-generation device architectures.

Nevertheless, despite these promising advantages, the widespread adoption of Ge still faces multiple material and interface challenges that remain unresolved. One of the most critical obstacles is the severe Fermi-level pinning effect at the Ge/dielectric interface, which significantly degrades the contact properties and increases the effective Schottky barrier height, thereby limiting current injection efficiency. In addition, the native germanium oxide (GeOx) formed on the surface of Ge is chemically unstable and exhibits poor dielectric quality. This instability often results in the generation of a high interface trap density (Dit) at the Ge/oxide interface, which in turn deteriorates the subthreshold characteristics, increases leakage current, and impedes the realization of high-performance Ge-based MOSFETs. These issues, unless properly mitigated, impose severe restrictions on the further development of Ge channel devices.

In light of these challenges, our laboratory has pursued an alternative materials engineering route by fabricating high-quality germanium-on-insulator (GeOI) wafers through wafer bonding techniques. The resulting GeOI substrates exhibit excellent thin-film characteristics, such as uniform thickness, reduced defect density, and enhanced surface smoothness. The fabrication of GeOI represents an important milestone because it not only overcomes the limitations associated with bulk Ge substrates but also provides a viable platform for integrating Ge devices into advanced CMOS process flows. Most importantly, the superior film quality of GeOI enables the demonstration of outstanding electrical properties at relatively low processing temperatures, indicating that high-performance Ge-based transistors operating in low-thermal-budget regimes are indeed feasible.

To further address the issue of interface defect reduction, this study focused on a systematic exploration of interface engineering strategies aimed at improving the Ge/dielectric interface quality. The research began with an ozone (O₃)-based surface oxidation treatment, which provides a thin and uniform interfacial oxide layer. Following this initial oxidation, two distinct nitridation methods were employed to passivate the interface: (i) ammonia (NH₃) plasma nitridation and (ii) hydrazine (N₂H₄) chemical nitridation. For evaluating the electrical performance of these interface treatments, fin-type field-effect transistors (FinFETs) were selected as the test vehicle, owing to their superior electrostatic control and their relevance to advanced technology nodes.

During the nitridation process, the initial GeOx interfacial layer undergoes a chemical transformation into germanium oxynitride (GeON). This transformation has a pronounced effect on the electrical characteristics of the device. While the introduction of nitrogen helps to suppress some defects, it also has the potential to aggravate leakage current behavior if not properly optimized. Indeed, the presence of GeON may significantly alter the band alignment and carrier transport mechanisms at the interface, leading to noticeable variations in leakage pathways. Therefore, a critical part of this work is the careful examination of how the nitridation step impacts device reliability, particularly under low-temperature operation conditions, where variability effects can be magnified.

The two nitridation methods used in this study differ fundamentally in their underlying mechanisms. The first approach, hydrazine (N₂H₄) nitridation, relies on the thermal decomposition of N₂H₄ gas to provide reactive nitrogen species. Although this method can potentially deliver high nitrogen incorporation, its effectiveness becomes increasingly limited when applied to extremely scaled devices with small critical dimensions, where incomplete nitridation may occur. Such incomplete passivation can leave portions of the interface unprotected, giving rise to localized defects and higher leakage currents. On the other hand, the second approach, ammonia (NH₃) plasma nitridation, generates energetic nitrogen species via plasma discharge, which bombard the surface and incorporate into the interfacial oxide. While this method can achieve more uniform surface modification, the plasma bombardment effect may introduce additional surface damage. As a consequence, at low processing temperatures, the combination of ozone oxidation followed by NH₃ plasma nitridation (O₃ + NH₃) demonstrates more pronounced variability, as the plasma-induced damage competes with the passivation benefit.

Taken together, the comparative analysis of these two nitridation techniques provides crucial insights into the trade-offs between chemical completeness and physical damage, both of which strongly influence the interface quality and device performance. By evaluating the electrical characteristics of FinFET test structures subjected to different treatments, this research sheds light on the optimal interface engineering strategies required to unlock the full potential of Ge channel devices. Ultimately, the findings highlight both the opportunities and the challenges that accompany the transition from Si to Ge, reinforcing the importance of continued research into Ge surface passivation, interface stability, and low-temperature processing for future semiconductor technologies.

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