隨著半導體技術持續朝向高效能與更微小製程節點發展，積體電路（IC）製造流程的複雜性也大幅提升。隨著電晶體不斷微型化，製程步驟顯著增加，對製程波動與缺陷的敏感度也同步提高，導致維持製程穩定性與達成理想良率成為當前先進製程中的關鍵挑戰。為此，本研究提出一套輕量化的整合式優化框架DOE-ML-HA，整合實驗設計（Design of Experiment, DOE）、機器學習（Machine Learning, ML）與啟發式演算法（Heuristic Algorithm, HA）等多項技術，形成一套系統性的解決方法。此框架具備以最少實驗次數建構預測模型的能力。本研究將 DOE-ML-HA 框架應用於優化IC半導體製造製程中醫療設備的電阻特性。成功辨識出最佳製程參數設定，將電阻值由 191.1 × 10⁻³ Ω改善至 176.84 × 10⁻³ Ω，接近目標值 176.5 × 10⁻³ Ω。此外，該框架亦有效降低 DRAM 元件中五種 Ti 薄膜厚度的電阻偏差，分別改善了 86.8%、94.1%、95.9%、98.2% 與 98.8%。本框架具備於資源受限及低功耗運算平台上運行的能力，可實現製程參數的即時動態調整，使 IC 製造商能夠迅速應對製程變異並有效提升產品品質。

As semiconductor technology continues to evolve toward higher performance and smaller feature sizes, the complexity of integrated circuit (IC) fabrication processes has escalated significantly. The ongoing miniaturization of transistors had introduced additional processing steps and heightened sensitivity to process fluctuations and defects, presenting critical challenges in maintaining process stability and achieving desirable yield outcomes. In response to these issues, this study introduced a lightweight integrated optimization framework, referred to as DOE-ML-HA, which integrates design of experiment (DOE), machine learning (ML), and heuristic algorithm (HA) into a cohesive methodology. The proposed framework was capable of developing predictive models using a minimal number of experimental runs. This study applied the DOE-ML-HA framework to optimize resistance characteristics of medical devices within IC semiconductor manufacturing processes. The framework successfully identified the optimal set of process parameters, reducing the resistance from 191.1 × 10⁻³ Ω to 176.84 × 10⁻³ Ω, closely approaching the target value of 176.5 × 10⁻³ Ω. Furthermore, it effectively minimized resistance deviations across five Ti thin film thicknesses in DRAM components, achieving improvements of 86.8%, 94.1%, 95.9%, 98.2%, and 98.8%, respectively. The framework was capable of operating on resource-constrained and low-power computing platforms, enabling real-time dynamic adjustment of process parameters. This capability allowed IC manufacturers to react quickly to process variations and significantly enhance product quality.

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