本論文中，第一個部份我們針對不同應力形變之金氧半場效電晶體低頻雜訊(1/f 雜訊)進行研究及探討，從而了解不同應變矽工程下低頻雜訊之響應。透過低頻雜訊分析，除可觀測不同應變技術對於元件介面特性影響外，並能進一步闡述應變矽元件低頻雜訊的物理機制。論文區分兩大主題進行探討:單軸伸張應變矽記憶技術之n型金氧半場效電晶體與單軸壓縮應變矽鍺源汲極之p型金氧半場效電晶體。
對於具有單軸伸張應變記憶技術之n型金氧半場效電晶體來說，根據實驗結果顯示採用應變記憶技術，可有效將單軸伸張應力傳遞至元件通道，進而使得n型金氧半場效電晶體之驅動電流能夠被有效提升，並且透過1/f雜訊與隨機擾動雜訊分析，發現雖然比傳統元件多增加一道製程程序，但並未對介面特性產生嚴重退化。另一方面，我們觀察到使用單軸伸張應變記憶技術之n型金氧半場效電晶體在正規化頻譜圖中有明顯的改善，進而發現伸張應變能夠有效降低穿隧衰退長度以及庫倫散射，因此能有效改善其低頻雜訊品質。另一方面，在具有單軸壓縮應變矽鍺源汲極之p型金氧半場效電晶體，我分發現隨著源汲極鍺濃度的提升，電晶體之驅動電流能夠被有效提升，透過1/f雜訊與隨機擾動雜訊進一步的分析，我們也觀察到矽鍺源汲極所產生之單軸壓縮應變能夠有效降低穿隧衰退長度，因此也能有效改善p型金氧半場效電晶體其低頻雜訊品質。
第二個部份，我們利用二氧化鋯與二氧化鉿兩種高介電係數材料來製作金氧半場效電晶體的閘極氧化層，在n型金氧半場效電晶體中，我們發現利用二氧化鋯製作之場效電晶體驅動飽和電流比使用二氧化鉿所製作之場效電晶體較高，並且進一步透過1/f雜訊與隨機擾動雜訊的分析，二氧化鋯場效電晶體雜訊較二氧化鉿場效電晶體小，並且作用的缺陷位置在緩衝介面層中(二氧化矽)，而二氧化鉿場效電晶體缺陷位置則位於高介電係數閘極氧化層中，這使的兩種元件的雜訊行為與產生機制不同。另一方面，在p型金氧半場效電晶體中，我們發現分別利用兩種製作之金氧半場效電晶體，在驅動飽和電流的部分趨近於相同無明顯變化，經過1/f雜訊與隨機擾動雜訊量測與分析，發現缺陷都位於高介電係數閘極氧化層中並且深度十分接近，這使得p型金氧半場效電晶體中未獲得良好的改善。

In this dissertation, we investigate the low frequency noise (1/f noise) characterization of Si/SiO2 interface properties in strained-Si CMOS transistors. By utilizing the 1/f noise analysis, we can understand the response of interface properties in different strain technique transistors. The experiment of this dissertation is divided into three parts. First, we used 1/f noise to evaluate stress-memorization technique (SMT) induced-stress in nMOS and embedded SiGe S/D pMOS is investigated. As compared to device without SMT process, the comparable 1/f noise level obtained from strained Si nMOS with the SMT process indicates that adding the SMT process will not affect the Si/SiO2 interface quality. Moreover, it is observed that the normalized input-referred voltage noise spectral density (LSVG) of 28-nm SMT nMOSFETs is four times lower than 1 m SMT nMOSFEs. It presents an intrinsic benefit of 1/f noise behavior stemming from SMT-induced more strain in short channel because it can reduce tunneling attenuation length and Coulomb scattering coefficient. As in pMOS, the purpose of implementing tip-shaped SiGe S/D is to further increase channel stress because it provides a closer proximity of embedded SiGe to the channel. By characterizing RTN, we found that the pMOS underwent uniaxial compressive strain that was provided by tip-shaped SiGe S/D, and the trap energy level being close to the channel valence band resulted in the trap located close to the Si/SiO2 interface, as compared with the control device without embedded SiGe S/D.
Finally, we investigated the trap behavior in nMOS with different HK gate dielectrics (i.e., HfO2 and ZrO2) by using 1/f noise and RTN measurements simultaneously. Compared with the HfO2 nMOS, a considerably lower 1/f noise level was observed in ZrO2 nMOS, resulting from the decrease in λ and Nt. It was found that the xt of ZrO2 nMOS is in close proximity to the IL/Si interface as well. On the other hand, compared with the HfO2 nMOS, a considerably higher 1/f noise level was observed in ZrO2 nMOSFETs, resulting from the increase in λ. But, in the pMOS, compared with the ZrO2 pMOS, a considerably lower 1/f noise level was observed in HfO2 pMOS, resulting from the decrease in λ and Nt. The lower Nt is attributed so that HfO2 device has a better interface property. Although RTN measurement only reflects the active locations of trap which are in the HK dielectric, the lower trap density is sufficient to support the investigation of 1/f noise result.

[1.1] N. Mohta, and S. E. Thompson, “Mobility Enhancement”, IEEE Circuits and Devices Magazine, Vol. 21, pp. 18–23, 2005.
[1.2] S. Takagi, T. Irisawa, T. Tezuka, T. Numata, S. Nakaharai, N. Hirashita, Y. Moriyama, K. Usuda, E. Toyoda, S. Dissanayake, M. Shichijo, R. Nakane, S. Sugahara, M. Takenaka, and N. Sugiyama, “Carrier-transport-enhanced channel CMOS for improved power consumption and performance”, IEEE Trans. Electron Devices, Vol. 55, pp. 21–39, 2008.
[1.3] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H. S. Wong, “Device scaling limits of Si MOSFETs and their application dependencies”, Proc. of the IEEE, Vol. 89, pp. 259–288, 2001.
[1.4] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits”, Proc. of the IEEE, Vol. 91, pp. 305–327, 2003.
[1.5] H. Shang, M. M. Frank, E. P. Gusev, J. O. Chu, S. W. Bedell, K. W. Guarini, and M. Leong, “Germanium channel MOSFETs: opportunities and challenges”, IBM J. Res. and Dev., Vol. 50, pp. 377–386, 2006.
[1.6] J. S. Goo, Q. Xiang, Y. Takamura, F. Arasnia, E. N. Paton, P. Besser, J. Pan, and M. R. Lin, “Band offset induced threshold variation in strained-Si nMOSFETs”, IEEE Electron Device Lett., Vol. 24, pp. 63 568–570, 2003.
[1.7] The International Technology Roadmap for Semiconductors (ITRS), Semiconductor Ind. Assoc., 2005.
[1.8] F. Ootsuka, S. Wakahara, K. Ichinose, A. Honzawa, S. Wada, H. Sato, T. Ando, H. Ohta, K. Watanabe, and T. Onai, “A highly dense, high-performance 130 nm node CMOS technology for large scale system-on-a-chip applications”, IEDM Tech. Dig., pp. 575-578, 2000.
[1.9] A. Shimizu, K. Hachimine, N. Ohki, M. Koguchi, Y. Nonaka, H. Sato, and F. Ootsuka, “Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement”, IEDM Tech. Dig., pp. 433-436, 2001.
[1.10] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffiann', K. Johnson', C. Kenyon, J. Klaus, B. Mclntyre, K. Mistry, A. Murthy, 1. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson and M. Bohr, “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors”, IEDM Tech. Dig., pp. 978-981, 2003.
[1.11] K. Ota, K. Sugihara, H. Sayama, T. Uchida, H. Oda, T. Eimori, H. Morimoto, and Y. Inoue, “Novel locally strained channel technique for high performance 55nm CMOS”, IEDM Tech. Dig., pp. 27-30, 2002.
[1.12] C. H. Chen, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J., Tao, Y. Jin, C. H. Diaz, S. C. Chen, and M. S. Liang, “Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application”, Symp. VLSI Tech. Dig., pp. 56-57, 2004.
[1.13] C. Ortolland, P. Morin, C. Chaton, E. Mastromatteo, C. Populaire, S. Orain, F. Leverd, P. Stolk, F. Boeuf, and F. Arnaud, “Stress Memorization Technique (SMT) Optimization for 45nm CMOS”, Symp. VLSI Tech. Dig., pp. 78-79, 2006.
[1.14] R. Chau, S. Datta, M. Doczy, J. Kavalieros, and M. Metz, “Gate Dielectric Scaling for High-Performance CMOS: from SiO2 to High-k”, Ext. Abst. of International Workshop on Gate Insulator (IWGI)., pp. 124-126, 2003
[1.15] S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFET’s”, IEEE Electron Device Letters, Vol. 18, no. 5, pp. 209-211, 1997
[1.16] http://www.semiconwest.org/cms/groups/public/documents/web_content/ctr_024403.pdf
[1.17] B. Yu, H. Wang, C. Riccobene, Q. Xiang; M. R. Lin,” Limits of gate-oxide scaling n nano-transistors”, in VLSI Symp. Tech. Dig., 2000, pp. 90-91.
[1.18] L.-A. Ragnarsson, L. Pantisano, V. Kaushik, S.-I. Saito, Y. Shimamoto, S. D. Gendt, M. Heyns, “The impact of sub monolayers of HfO/sub/ on the device performance of high-k based transistors”, IEDM Tech. Dig. pp. 4.2.1 - 4.2.4, 2003.
[1.19] D. A. Dallmann, K. Shenai, “Scaling constraints imposed by self-heating in submicron SOI MOSFET's”, IEEE Trans. Electron Dev. Vol. 42, 3, pp. 489 - 496, 1995.
[1.20] B. Razavi, “A study of phase noise in CMOS oscillators”, IEEE J. Solid-State Circuits, Vol. 31, pp. 331-343, 1996.
[1.21] M. J. Deen and O. Marinov, “Noise in advanced electronic devices and circuits”, in Proc. Int. Conf. Noise and Fluctuations (ICNF), 2005, pp. 3-12.
[1.22] L. K. J. Vandamme, “Noise as a diagnostic tool for quality and reliability of electronic devices”, IEEE Trans. Electron Devices, Vol. 41, pp. 2176-2187, 1994.
[1.23] C. Claeys and E. Simoen, “Impact of advanced processing modules on the lowfrequency noise performance of deep-submicron CMOS technologies”, Microelectron. Reliab., Vol. 40, pp. 1815-1821, 2000.
[1.24] A. D. van Rheenen, G. Bosman, and R. J. J. Zijlstra, “Low frequency noise measurements as a tool to analyze deep-level impurities in semiconductor devices”, Solid-State Electron., Vol. 30, pp. 259-265, 1987.
[1.25] R. Jayaraman and C. G. Sodini, “A 1/f noise technique to extract the oxide trap density near the conduction band edge of silicon”, IEEE Trans. Electron Devices, Vol. 36, pp. 1773-1782, 1989.
[1.26] M. J. Kirton and M. J. Uren, “Noise in solid-state microstructures: a new perspective on individual defects, interface states and low-frequency (1/f) noise”, Advances in Physics, Vol. 38, pp. 367-468, 1989.
[1.27] L. K. J. Vandamme, X. Li, and D. Rigaud, “1/f noise in MOS devices, mobility or number fluctuations ? ”, IEEE Trans. Electron Devices, Vol. 41, pp. 1936-1945, 1994.
[2.1] M. von Haartman, M. Östling, “Low-Frequency Noise in Advanced MOS Devices”, Springer, 2007.
[2.2] R. Landauer, “The noise is the signal”, Nature, Vol. 392, pp. 658-659, 1998.
[2.3] F. N. Hooge, “1/f Noise Sources”, IEEE Trans. Electron Devices, Vol. 41, pp.1926-1935, 1994.
[2.4] T. Musha, S. Sata and M. Yamamoto, “Noise in Physical Systems and 1/f Fluctuation”, IOS Press, Japan, 1992.
[2.5] A. van der Ziel. “Noise in Solid State Devices and Circuits.” John Wiley & Sons, New York, 1986.
[2.6] N. Giordano, “Defect motion and low-frequency noise in disordered metals”, Solid State Sci., Vol. 3, no. 1, p. 27, 1989.
[2.7] J. B. Johnson, “Thermal agitation of electricity in conductors”, Phys. Rev., Vol. 32, pp. 97-109, 1928.
[2.8] H. Nyquist, “Thermal agitation of electric charge in conductors”, Phys. Rev., Vol. 32, pp. 110-113, 1928.
[2.9] A. van der Ziel, J. B. Anderson, A. N. Birbas, W. C. Chen, P. Fang, V. M. Hietala, C. S. Parka, P. R. Pukite, M. F. T., X. Wua, J. Xu and A. C. Young, “Shot noise in solid state diodes”, Solid-State Electron, Vol. 29, p. 1069, 1986.
[2.10] K.K Hung, P.K. Ko, C.M. Hu,”A unified model for the flicker noise in metal-oxide -semiconductor field-effect transistors”, IEEE Trans. Electron Devices, p654, 1990.
[2.11] P. Dutta and P. M. Horn, “Low-frequency fluctuations in solids: 1/f noise”, Rev. Mod. Phys., 53, 497-516, 1981.
[2.12] F. N. Hooge, “1/f noise is no surface effect”, Phys. Lett. A, Vol. 29a, pp. 139-140, 1969.
[2.13] F. N. Hooge, “Discussion of recent experiments on 1/f noise”, Physica, Vol. 60, pp.130-144, 1972.
[2.14] F. N. Hooge, T. G. M. Kleinpenning, and L. K. J. Vandamme, “Experimental studies on 1/f noise”, Rep. Prog. Phys., Vol. 44, pp. 479-531, 1981.
[2.15] S. Machlup, “Noise in semiconductors: spectrum of a two-parameter random signal”, J. Appl. Phys., Vol. 25, pp. 341-343, 1954.
[2.16] Y. A. Allogo, M. Marin, M. de Murcia, P. Llinares, D. Cottin, “1/f noise in 0.18 m technology n-MOSFETs from subthreshold to saturation”, Solid-State Electronics, Vol. 46, pp. 977–983, 2002.
[2.17] G. Ghibaudo, O. Roux, C. Nguyen-Duc, F. Balestra, J. Brini, “Improved Analysis of Low Frequency Noise in Field-Effect MOS Transistors”, Phys. Stat. Sol. (A), Vol. 124, pp. 571-581, 1991.
[2.18] M.J. Kriton, M.J. Uren “Noise in solid-state microstructure: microstructure: A new perspective on individual defects interface states and low frequency noise”, Advances Physics, Vol.38, No.4, pp.367-468, 1989.
[2.19] M. O. Andersson, Z. Xiao, S. Norrman, O. Engström, “Model based on trap-assisted tunneling for two-level current fluctuations in submicrometer metal–silicon-dioxide–silicon diodes”, Phys. Rev. B, Vol.41, 9836, 1990.
[2.20] A. Avella, D. Schroeder, and W. Krautschneider, “Modeling random telegraph signals in the gate current of metal–oxide–semiconductor fieldeffect transistors after oxide breakdown”, Applied Physics, Vol.94, No.1, pp.703-708, 2003.
[2.21] K. S. Ralls, W. J. Skocpol, L. D. Jackel, R. E. Howard, L. A. Fetter, R. W. Epworthand D. M. Tennant, “Discrete Resistance Switching in Submicrometer Silicon Inversion Layers: Individual Interface Traps and Low-Frequency (1/f?) Noise”, Phys Rev. Lett., vol. 52, pp. 228-231, 1984.
[2.22] K. R. Farmer, C. T. Rogers, and R. A. Buhrman, “Localized-State Interactions in Metal-Oxide-Semiconductor Tunnel Diodes”, Phys. Rev. Lett., vol. 58, pp. 2255-2258, 1987.
[2.23] M. J. Kirton and M. J. Uren, “Noise in solid-state microstructures: a new perspective on individual defects, interface states and low-frequency (1/f) noise”, Adv. Phys., vol. 38, pp. 367-468, 1989.
[2.24] M. Schulz, “Coulomb energy of traps in semiconductor space-charge regions”, J. Appl. Phys., vol. 74, pp. 2649-2657, 1993.
[2.25] H. H. Mueller, D. Wörle, and M. Schulz, “Evaluation of the Coulomb energy for single-electron interface trapping in sub-μm metal-oxide-semiconductor field-effect transistors”, J. Appl. Phys., vol. 75, pp. 2970-2979, 1994.
[2.26] M. J. Chen and M. P. Lu, “On–off switching of edge direct tunneling currents in metal-oxide-semiconductor field-effect transistors”, Appl. Phys. Lett., vol. 81, pp. 3488-3490, 2002.
[2.27] S. Ferraton, L. Militaru, A. Souifi, S. Monfray, and T. Skotnicki, “Study of SiO2/Si interface properties of SON MOSFETs by random telegraph signal and charge pumping measurements”, Solid-State Electron., Vol. 52, 44, 2008.
[2.28] M. Trabelsi, L. Militaru, N. Sghaier, A. Savio, S. Monfray, and A. Souifi, “Study of Gate Oxide/Channel Interface Properties of SON MOSFETs by Random Telegraph Signal and Low Frequency Noise”, IEEE Trans. Nanotechnol., Vol. 10, 402, 2011.
[3.1] J. L. Liou, and F. Schwierz, “RF MOSFET: recent advances, current status and future trends”, Solid-State Electron., vol. 47, pp. 1881-1895, 2003.
[3.2] A. A. Abidi, “RF CMOS comes of age”, in Proc. Symp. VLSI Circuits, 2003, pp. 113-116.
[3.3] Y. Taur T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, Cambridge, 1998.
[3.4] R. F. Pierret, Field effect devices, Addison-Wesley, Reading, 1990.
[3.5] D. K. Ferry and K. Bird, Electronic materials and device, Academic Press, 2001.
[3.6] Y. Tsividis, Operation and modeling of the MOS transistor, Second Edition, Oxford University Press, New York, 2003.
[3.7] F. Schwierz, Hei Wong and J. J. Liou, Nanometer CMOS, Pan Stanford Publishing, Singapore, 2010.
[3.8] G. Ghibaudo, “New method for the extraction of MOSFET parameters”, Electronics Letters, vol. 24, pp. 543-545, 1988.
[3.9] S.C. Sun and J.D. Plummer, “Electron Mobility in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces”, IEEE Trans. Electron Dev., vol. ED-27, pp.1497–1508, 1980.
[3.10] R.V. Booth, M.H. White, H.S. Wong and T.J. Krutsick, “The Effect of Channel Implants on MOS Transistor Characterization”, IEEE Trans. Electron Dev., vol. ED-34, pp.2501–2509, 1987.
[3.11] G. Ghibaudo, “New method for the extraction of MOSFET parameters”, Electronics Letters, vol. 24, pp. 543-545, 1988.
[3.12] H.G. Lee, S.Y. Oh and G. Fuller, “A Simple and Accurate Method to Measure the Threshold Voltage of an Enhancement-Mode MOSFET”, IEEE Trans. Electron Dev. ED-29, 346–348, Feb. 1982.
[3.13] R. H. Dennard, F. H. Gaensslen, H. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion-implanted MOSFET’s with very small physical dimensions”, IEEE J. Solid-State Circuits, vol. SC-9, pp. 256–268, 1974
[3.14] R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. LeBlanc, “Ion implanted MOSFETs with very short channel lengths”, in IEDM Tech. Dig., 1973, pp. 152-155.
[3.15] D. L. Critchlow, “MOSFET scaling – the driver of VLSI technology”, Proc. of the IEEE, vol. 87, pp.659-667, 1999.
[3.16] S. Takagi, M. Iwase, and A. Toriumi, “On the universality of inversion-layer mobility in n- and p-channel MOSFETs”, in IEDM Tech. Dig., 1988, pp. 398-401.
[3.17] D. K. Nayak and S. K. Chun, “Low-field hole mobility of strained Si on (100) Si1–xGex substrate”, Appl. Phys. Lett. 64, pp. 2514-2516, 1994.
[3.18] T. Vogelsang and K. R. Hofmann, “Electron transport in strained Si layers on Si1−x Gex substrate”, Appl. Phys. Lett. 63, pp. 186-188, 1993.
[3.19] K. Rim, J. Chu, H. Chen, K.A. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott. K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chan. D. Boyd, M. Ieong, and H.-S. Wong, “Characteristics and Device Design of Sub-100 nm Strained Si N- and PMOSFETs”, in VLSI Symp. Tech. Dig., 2002, pp. 98-99.
[3.20] D. K. Nayak, J. C. S. Woo, J. S. Park, K. L. Wang, and K. P. MacWilliams, “High-mobility p-channel metal-oxide-semiconductor field-effect transistor on strained Si”, Appl. Phys. Lett. 62, 2853, 1993
[3.21] S. I. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, “Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal-oxide-semiconductor field-effect transistors”, J. Appl. Phys., vol. 80, pp. 1567–1577, Aug. 1996.
[3.22] Y. Sun, S. E. Thompson, and T. Nishida, “Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors”, J. Appl. Phys., vol. 101, pp. 104503, 2007.
[3.23] N. Mohta, and S. E. Thompson, “Mobility Enhancement”, IEEE Circuits and Devices Magazine, vol. 21, pp. 18–23, 2005
[3.24] K. Uchida, T. Krishnamohan, K. C. Saraswat, and Y. Nishi, “Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime”, in IEDM Tech. Dig., 2005, pp. 129–132.
[3.25] H. Irie, K. Kita, K. Kyuno, and A. Toriumi, “In-plane mobility anisotropy and universality under uniaxial strains in n- and p-MOS inversion layers on (100), (110), and (111) Si”, in IEDM Tech. Dig., 2004, pp. 225–228.
[3.26] S. I. Takagi, J. Koga, and A. Toriumi, “Subband structure engineering for performance enhancement of Si MOSFETs”, in IEDM Tech. Dig., 1997, pp. 219–222.
[3.27] S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, “Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs”, in IEDM Tech. Dig., 2004, pp. 221–224.
[3.28] S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, “A Logic Nanotechnology Featuring Strained-Silicon”, IEEE Electron Device Lett., vol. 25, pp. 191–193, 2004.
[3.29] S. Pidin, T. Mori, K. Inoue, S. Fukuta, N. Itoh, E. Mutoh, K. Ohkoshi, R. Nakamura, K. Kobayashi, K. Kawamura, T. Saiki, S. Fukuyama, S. Satoh, M. Kase, and K. Hashimoto, “A Novel Strain Enhanced CMOS Architecture Using Selectively Deposited High Tensile And High Compressive Silicon Nitride Films”, in Tech. Dig. IEDM, 2004, pp. 213-216.
[3.30] S. Orain, V. Fiori, D. Villanueva, A. Dray, and C. Ortolland, “Method for managing the stress due to the strained nitride capping layer in MOS transistors”, in IEEE Tran. Electron Devices, vol. 54, no. 4, April 2007.
[3.31] K.-W. Ang, K.-J. Chui, V. Bliznetsov, Y. Wang, L.-Y. Wong, C.-H. Tung, N. Balasubramanian, M.-F. Li, G. Samudra, and Yee-Chia Yeo, “Thin Body Silicon-on-Insulator N-MOSFET with Silicon-Carbon Source/Drain Regions for Performance Enhancement”, in Tech. Dig. IEDM, 2005, pp. 497 - 500.
[3.32] Y. Jeon, G.C. F. Yeap, P. Grudowski, T. Van Gompel, J. Schmidt, M. Hall, B. Melnick, M. Mendicino, S. Venkatesan, “The impact of STI mechanical stress on the device performance of 90 nm technology node with different substrates and isolation processes”, in VLSI Symp. Tech. Dig., 2003, pp. 164-165.
[3.33] C. Le Cam, F. Guyader, C. de Buttet, P. Guyader, G. Ribes, M. Sardo, S. Vanbergue, F. Boeuf, F. Arnaud, E. Josse, M. Haond, “A low cost drive current enhancement technique using shallow trench isolation induced stress for 45-nm node”, in VLSI Symp. Tech. Dig., 2006, pp. 82 - 83.
[3.34] P. R. Chidambaram, C. Bowen, S. Chakravarthi, C. Machala, and R. Wise, “Fundamentals of Silicon Material Properties for Successful Exploitation of Strain Engineering in Modern CMOS Manufacturing”, IEEE Trans. Elect. Device., vol. 53, pp. 944-964, 2006.
[3.35] A. Steegen, K. Maex, “Silicide-induced stress in Si: origin and consequences for MOS technologies”, in Mater. Sci. and Eng. R, pp. 1-53, 2002.
[3.36] C. Ortolland, P. Morin, C. Chaton, E. Mastromatteo, C. Populaire, S. Orain, F. Leverd, P. Stolk, F. Boeuf and F. Arnaud, “Stress Memorization Technique (SMT) Optimization for 45nm CMOS”, in VLSI Symp. Tech. Dig., 2006, pp. 78 - 79.
[3.37] C. Ortolland, Y. Okuno, P. Verheyen, C. Kerner, C. Stapelmann, M. Aoulaiche, N. Horiguchi, and T. Hoffmann, “Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process”, IEEE Trans. Elect. Device., vol. 56, pp. 1690-1697, 2009.
[4.1] Y. Kimira, M. Kishi, and T. Katoda, “Effects of elastic stressintroduced by a silicon nitride cap on solid-phase crystallization ofamorphous silicon”, J. Appl. Phys., vol. 86, pp. 2278–2280, 1999.
[4.2] T. Miyashita, T. Owada, A. Hatada, Y. Hayami, K. Ookoshi, T. Mori, H. Kurata, and T. Futatsugi, “Physical and electrical analysis of the stress memorization technique (SMT) using poly-gates and itsoptimization for beyond 45-nm high-performance applications”, IEDM Tech. Dig., pp. 1– 4, 2008.
[4.3] A. Eiho, T. Sanuki, E. Morifuji, T. Iwamoto, G. Sudo, K. Fukasaku, K. Ota, T. Sawada, O. Fuji, H. Nii, M. Togo, K. Ohno, K. Yoshida, H. Tsuda, T. Ito, Y. Shiozaki, N. Fuji, H. Yamazaki, M. Nakazawa, S. Iwasa, S. Muramatsu, K. Nagaoka, M. Iwai, M. Ikeda, M. Saito, H. Naruse, Y. Enomoto, S. Kitano, S. Yamada, K. Imai, N. Nagashima, T. Kuwata, and F. Matsuoka, “Management of Power and Performance with Stress Memorization Technique for 45nm CMOS”, Symp. VLSI Tech. Dig., pp.218-219, 2007.
[4.4] A. Wei, M. Wiatr, A. Mowry, A. Gehring, R. Boschke, C. Scott, J. Hoentschel, S. Duenkel, M. Gerhardt, T. Feudel, M. Lenski, F. Wirbeleit, R. Otterbach, R. Callahan, G. Koerner, N. Krumm, D. Greenlaw, M. Raab, and M. Horstmann, “Multiple Stress Memorization In Advanced SOI CMOS Technologies”, Symp. VLSI Tech. Dig., pp.216-217, 2007.
[4.5] C. H. Chen, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J., Tao, Y. Jin, C. H. Diaz, S. C. Chen, and M. S. Liang, “Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application”, Symp. VLSI Tech. Dig., pp. 56-57, 2004.
[4.6] S. Fang, S. S. Tan, J. Yuan, Q. Liang, T. Dyer, R. Robinson, J. Liu, J. J. Kim, B. Zuo, M. Belyansky, J. Yan, Z. Luo, J. Li, Y. Wang, B. Greene, H. Ng, Y. Li, H. Shang, E. Maciejewski, M. Yang, R. Divakaruni, E. Leobandung, and J. Jagannathan, “SMT and enhanced SPT with Recessed SD to Improve CMOS Device Performance”, Solid-State and Integrated-Circuit Technology, pp. 117-120, 2008.
[4.7] P. Morina, C. Ortollandc, E. Mastromatteoc, C. Chatonb and F. Arnauda, “Mechanisms of stress generation within a polysilicon gate for nMOSFET performance enhancement”, Materials Science and Engineering: B, pp. 215-219, 2005.
[4.8] K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan, T. Ghani, T. Hoffmann, A. Murthy, J. Sandford, R. Shaheed, K. Zawadzki, K. Zhang, S. Thompson, and M. Bohr, “Delaying Forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology”, in VLSI Symp. Tech. Dig., pp. 50-51, 2004.
[4.9] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. Mclntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson and M Bohr, ”A 90 High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors”, in IEDM Tech Dig., pp. 978-980, 2003.
[4.10] P. Fantini and G. Ferrari, “Low frequency noise and technology induced mechanical stress in MOSFETs”, Microelectron. Rel., vol. 47, no. 8, pp. 1218–1221, Aug. 2007.
[4.11] M. H. Lin, E. R. Hsieh, S. E. Chung, C. H. Tsai, P. W. Liu, Y. H. Lin, C. T. Tsai, and G. H. Ma, “A new observation of strain-induced slow traps in advanced CMOS technology with process-induced strain using random telegraph noise measurement”, in VLSI Symp. Tech. Dig., 2009, pp. 52–53.
[4.12] N. Tamura, Y. Shimamune, and H. Maekawa, “Embedded silicon germanium (eSiGe) technologies for 45 nm nodes and beyond”, in Proc. IEEE IWJT, 2008, pp. 73–77.
[4.13] C. Leyris, F. Martinez, A. Hoffmann, M. Valenza, and J. C. Vildeuil, “N-MOSFET oxide trap characterization induced by nitridation process using RTS noise analysis”, Microelectron. Rel., vol. 47, no. 1, pp. 41–45, Jan. 2007.
[4.14] S. Kobayashi, M. Saitoh, and K. Uchida, “Id fluctuations by stochastic single-hole trappings in high-k dielectric p-MOSFETs”, in VLSI Symp. Tech. Dig., 2008, pp. 78–79.
[4.15] Y. T. Hou, M. F. Li, Y. Jin, and W. H. Lai, “Direct tunneling hole currents through ultrathin gate oxides in metal-oxide-semiconductor devices”, J. Appl. Phys., Vol. 91, pp. 258-264, Jan. 2002.
[4.16] S. E. Thompson, P. Packan, and M. Bohr, “MOS scaling: transistor challenges for the 21st century”, Intel Tech. Journal, pp. 1-19, 1998.
[4.17] X. Yang, J. Lim, G. Sun, K. Wu, T. Nishida, and S. E. Thompson, “Strain-induced changes in the gate tunneling currents in p-channel metal-oxide-semiconductor field-effect transistors”, Appl. Phys. Lett., Vol. 88, pp. 052108-1-3, Jan. 2006.
[4.18] K. Alam, S. Zaman, M. M. Chowdhury, M. R. Khan, and A. Haque, “Effects of inelastic scattering on direct tunneling gate leakage current in deep submicron metal-oxide-semiconductor transistors”, J. Appl. Phys., Vol. 92, pp. 937–943, Jul.2002.
[4.19] X. Yang, Y. Choi, T. Nishida, and S. E. Thompson, “Gate direct tunneling currents in uniaxial stressed MOSFETs”, in Proc. Of EDST, pp. 149-152, 2007.
[4.20] S. I. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, “Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal oxide semiconductor field-effect transistors”, J. Appl. Phys., Vol. 80, pp. 1567-1577, Aug. 1996.
[4.21] T. J. Wang. “Investigation of Uniaxial Strain Technology on the Characteristics of Nanoscale CMOS and Bipolar Transistors”, Dissertation of NCKU, 2008.
[4.22] X. Yang, Y. Choi, T. Nishida, and S. E. Thompson, “Gate direct tunneling currents in uniaxial stressed MOSFETs”, in Proc. of EDST, 2007, pp. 149–152.
[4.23] S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, “Uniaxial-process -induced strained-Si: extending the CMOS roadmap”, IEEE Trans. Electron Devices, vol. 53, pp. 1010–1020, May, 2006.
[4.24] G. Ghibaudo, T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices”, Microelectronics Reliability Vol.42, pp. 573-582, 2002.
[4.25] P. C. Huang , S. L. Wu, S. J. Chang, Y. T. Huang, C. T. Lin, M. Mac, O. Cheng,” Electrical characteristics of nMOSFETs fabricated on hybrid orientation substrate with amorphization/templated recrystallization method”, Microelectronics Reliability, Vol.50 , pp. 662-665, 2010.
[4.26] Y. T. Huang, S. L. Wu, S. J. Chang, , C. W. Kuo, Y. T. Chen, Y. C. Cheng, and O. Cheng,” Dependence of DC Parameters on Layout and Low-Frequency Noise Behavior in Strained-Si nMOSFETs Fabricated by Stress-Memorization Technique.”, IEEE Electron Device Lett., Vol. 31, NO. 5, May 2010.
[4.27] C. W. Kuo, S. L. Wu, S. J. Chang, Y. T. Huang, Y. C. Cheng, and O. Cheng,” Impact of stress-memorization technique induced-tensile strain on low frequency noise in n-channel metal-oxide-semiconductor transistors”, Appl. Phys. Lett. Vol. 97,2010
[4.28] L. K. J. Vandamme, X. Li, and D. Rigaud, “l/f Noise in MOS Devices, Mobility or Number Fluctuations?”, IEEE Trans. Electron Devices, Vol. 41, NO. 11, Nov. 1994.
[4.29] L. K. J. Vandamme and F. N. Hooge, “What Do We Certainly Know About 1/f Noise in MOSTs ?”, IEEE Trans. Electron Devices, Vol. 55, NO. 11, Nov. 2008.
[4.30] F. Crupi, P. Srinivasan, P. Magnone, E. Simoen, C. Pace, D. Misra, and C. Claeys, “Impact of the Interfacial Layer on the Low-Frequency Noise (1/f) Behavior of MOSFETsWith Advanced Gate Stacks”, IEEE Trans. Electron Devices, Vol. 27, NO. 8, Aug. 2006.
[4.31] J. J. Y. Kuo, W. P. N. Chen, and P. Su, “Impact of Uniaxial Strain on Low-Frequency Noise in Nanoscale PMOSFETs”, IEEE Electron Device Lett. Vol. 30, NO. 6, Jun. 2009.
[4.32] S. Ferraton, L. Militaru, A. Souifi, S. Monfray, and T. Skotnicki, “Study of SiO2/Si interface properties of SON MOSFETs by random telegraph signal and charge pumping measurements”, Solid-State Electron. 52, 44, 2008.
[4.33] M. Trabelsi, L. Militaru, N. Sghaier, A. Savio, S. Monfray, and A. Souifi, “Study of Gate Oxide/Channel Interface Properties of SON MOSFETs by Random Telegraph Signal and Low Frequency Noise”, IEEE Trans. Nanotechnol. 10, 402, 2011.
[4.34] G. Ghibaudo and T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices”, Microelectron. Reliab. 42,573, 2002.
[4.35] J. J. Y. Kuo, W. P. N. Chen, and P. Su, “A Comprehensive Investigation of Analog Performance for Uniaxial Strained PMOSFETs”, IEEE Electron Device Lett. 30, 672, 2009.
[4.36] M. V. Haartman and M. Ostling: Low-Frequency Noise in Advanced MOS Devices (Springer, Heidelberg, 2007) p. 47.
[4.37] M. J. Kirton and M. J. Uren, “Noise in solid-state microstructures: A new perspective on individual defects, interface states and low-frequency (1/ƒ) noise”, Adv. Phys. 38, 367, 1989.
[4.38] N. Tamura and Y. Shimamune, “45 nm CMOS technology with low temperature selective epitaxy of SiGe”, Appl. Surf. Sci. 254, 6067, 2008.
[4.39] M. Trabelsi, L. Militaru, N. Sghaier, A. Souifi, and N. Yacoubi, “Traps centers impact on Silicon nanocrystal memories given by Random Telegraph Signal and low frequency noise”, Solid-State Electron. , Vol. 56, 1, 2011.
[5.1] Y.-C. Yeo, T.-J. King, and C. Hu, “MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations,” IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 1027-1035, Apr. 2003.
[5.2] Y.-C. Yeo, Q. L., W. C. Lee, T.-J. King, C. Hu, X. Wang, X. Guo, and T. P. Ma, “Direct Tunneling Gate Leakage Current in Transistors with Ultrathin Silicon Nitride Gate Dielectric,” IEEE Electron Device Lett., vol. 20, no. 11, pp. 540-542, Nov. 2000.
[5.3] H. Hwang, W. Ting, B. Maiti, D.‐L. Kwong, and J. Lee, “Electrical characteristics of ultrathin oxynitride gate dielectric prepared by rapid thermal oxidation of Si in N2O,” Appl. Phys. Lett., vol. 57, no. 10, p. 1010, 1990.
[5.4] J. P. Chang and Y.-S. Lin, “Dielectric property and conduction mechanism of ultrathin zirconium oxide films,” Appl. Phys. Lett., vol. 79, no. 22, p. 3666, 2001.
[5.5] D. Lim, R. Haight, M. Copel, and E. Cartier, “Oxygen defects and Fermi level location in metal-hafnium oxide-silicon structures,” Appl. Phys. Lett., vol. 87, no. 7, p. 072902, 2005.
[5.6] L. Kang, B. H. Lee, W.-J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi, and J. C. Lee, “Electrical Characteristics of Highly Reliable Ultrathin Hafnium Oxide Gate Dielectric,” IEEE Electron Device Lett., vol. 21, no. 4, pp. 181-183, Apr. 2000.
[5.7] J. Kolodzey, E. A. Chowdhury, T. N. Adam, G. Qui, I. Rau, J. O. Olowolafe, J. S. Suehle, and Yuan Chen, “Electrical Conduction and Dielectric Breakdown in Aluminum Oxide Insulators on Silicon,” IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 121-128, Jan. 2000.
[5.8] S. Guha, E. Cartier, M. A. Gribelyuk, N. A. Bojarczuk, and M. C. Copel, “Atomic beam deposition of lanthanum- and yttrium-based oxide thin films for gate dielectrics,” Appl. Phys. Lett., vol. 77, no. 17, p. 2710, Oct. 2000.
[5.9] C. Auth, A. Cappellani, J.-S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, N. Rahhal-orabi, P. Ranade, J. Sandford, L. Shifren, V. Souw, K. Tone, F. Tambwe, A. Thompson, D. Towner, T. Troeger, P. Vandervoorn, C. Wallace, J. Wiedemer, C. Wiegand, “45nm High-k + Metal Gate Strain-Enhanced Transistors,” Dig. Tech. Pap. - Symp. VLSI Technol., pp. 128-129, 2008.
[5.10] C.-H. Jan, P. Bai, S. Biswas, M. Buehler, Z.-P. Chen, G. Curello, S. Gannavaram, W. Hafez, J. He, J. Hicks, U. Jalan, N. Lazo, J. Lin, N. Lindert, C. Litteken, M. Jones, M. Kang, K. Komeyli, A. Mezhiba, S. Naskar, S. Olson, J. Park, R. Parker, L. Pei, I. Post, N. Pradhan, C. Prasad, M. Prince, J. Rizk, G. Sacks, H. Tashiro, D. Towner, C. Tsai, Y. Wang, L. Yang, J.-Y. Yeh, J. Yip, K. Mistry, “A 45nm Low Power System-On-Chip Technology with Dual Gate (Logic and I/O) High-k/Metal Gate Strained Silicon Transistors,” Tech. Dig. - Int. Electron Devices Meet., pp. 637-640, 2008.
[5.11] Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices, Cambridge, 1998
[5.12] R. H. Dennard, F. H. Gaensslen, H-N, Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc,"Design of ion-implanted MOSFET’s with very small physical dimensions," IEEE J. Solid-State Circuits, vol. SC-9, pp. 256-268, 1974
[5.13] International Technology Roadmap for Semiconductor (ITRS), 2009
[5.14] ftp://download.intel.com/technology/architecture-silicon/ISSCC_09_plenary_bohr_present ation.pdf
[5.15] S. M. Sze, and K. K. Ng, Physics of Semiconductor Devices 3rd Edition, John Wiley & Sons, Inc., 2007
[5.16] IEDM 2010 Short Course: Reliability
[5.17] R. Chau, S. Datta, M. Doczy, J. Kavalieros, and M. Metz, “Gate Dielectric Scaling for High-Performance CMOS: from SiO2 to High-k,” Ext. Abst. of International Workshop on Gate Insulator (IWGI)., pp. 124-126, 2003
[5.18] S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFET’s,” IEEE Electron Device Letters, vol. 18, no. 5, pp. 209-211, 1997
[5.19] http://www.semiconwest.org/cms/groups/public/documents/web_content/ctr_024403.pdf
[5.20] T. Hattori, T .Yoshida, T. Shiraishi, K. Takahashi, H. Nohira, S. Joumori, K. Nakajima, M. Suzuki, K. Kimura, I. Kashiwagi, O. Oshima, S. Ohmi, and H. Iwai, “Composition, chemical tructure, and electronic band structure of rare earth oxide/Si(100) interface transition layer,” icroelectronic Engineering, vol. 72, pp. 283-287, 2004
[5.21] T. Ando, M. M. Frank, K. Choi, C. Choi, J. Bruley, M. Hopstaken, M. Copel, E. Cartier, . Kerber, A. Callegari, D. Lacey, S. Brown, Q. Yang, and V. Narayanan, “Understanding obility Mechanisms in Extremely Scaled HfO2 (EOT 0.42 nm) Using Remote Interfacial ayer Scavenging Technique and Vt-tuning Dipoles with Gate-First Process,” IEDM Tech.Dig., pp.423-426, 2009
[5.22] P. Ranade, T. Ghani, K. Kuhn , K. Mistry, S. Pae, L. Shifren, M. Stettler, K. Tone, S. Tyagi and M. Bohr, "High Performance 35nm LGATE CMOS Transistors Featuring NiSi Metal Gate (FUSI), Uniaxial Strained Silicon Channels and 1.2nm Gate Oxide," IEDM Tech. Dig., p. 217-220, 2005.
[5.23] L.-Å. Ragnarsson, Z. Li, J. Tseng, T. Schram, E. Rohr, M. J. Cho, T. Kauerauf, T. Conard, Y. Okuno, B. Parvais, P. Absil, S. Biesemans, and T. Y. Hoffmann, "Ultralow-EOT (5 Å) Gate-First and Gate-Last High Performance CMOS Achieved by Gate-Electrode Optimization," IEDM Tech. Dig., pp. 663-666, 2009.
[5.24] F. Arnaud, J. Liu, Y. M.Lee, K. Y.Lim, S. Kohler, J. Chen, B. K. Moon, C. W. Lai, M. Lipinski, L. Sang, F. Guarin, C. Hobbs, P. Ferreira, K. Ohuchi, J. Li, H. Zhuang, P. Mora, Q. Zhang, D. R. Nair, D. H. Lee, K. K. Chan, S. Satadru, S. Yang, J. Koshy, W. Hayter, M. Zaleski, D. V. Coolbaugh, H. W. Kim, Y. C. Ee, J. Sudijono, A. Thean, M Sherony, S. Samavedam, M. Khare, C. Goldberg, and A. Steegen, "32nm General Purpose Bulk CMOS Technology for High Performance Applications at Low Voltage," IEDM Tech. Dig., pp. 633-636, 2008.
[5.25] T. Tomimatsu, Y. Goto, H. Kato, M. Amma, M. Igarashi, Y. Kusakabe, M. Takeuchi, S.Ohbayashi, S.Sakashita, T. Kawahara, M. Mizutani, M. Inoue, M. Sawada, Y. Kawasaki, S. Yamanari, Y. Miyagawa, Y. Takeshima, Y. Yamamoto, S. Endo, T. Hayashi, Y. Nishida, K. Horita, T. Yamashita, H. Oda, K. Tsukamoto, and Y. Inoue, "Cost-effective 28nm LSTP CMOS Using Gate-First Metal Gate/High-k Technology," VLSI Tech. Dig., pp. 36-37, 2009.
[5.26] H. R. Harris, P. Kalra, P. Majhi, M. Hussain, D. Kelly, J. Oh, D. He, C. Smith, J. Barnett, P. D. Kirsch, G. Gebara, J. Jur, D. Lichtenwalner, A. Lubow, T. P. Ma, G. Sung, S. Thompson, B. H. Lee, H.-H. Tseng and R. Jammy, "Band-engineered Low PMOS VT with High-k/Metal Gates Featured in a Dual Channel CMOS Integration Scheme," VLSI Tech. Dig., pp. 154-155, 2007.
[5.27] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks , R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” IEDM Tech. Dig., pp. 247–250, 2007
[5.28] K. Choi, H. Jagannathan, C. Choi, L. Edge, T. Ando, M. Frank, P. Jamison, M. Wang, E. Cartier, S. Zafar, J. Bruley, A. Kerber, B. Linder, A. Callegari, Q. Yang, S. Brown, J. Stathis, J. Iacoponi, V. Paruchuri, and V. Narayanan, "Extremely Scaled Gate-First High-k/Metal Gate Stack with EOT of 0.55nm Using Novel Interfacial Layer Scavenging Techniques for 22nm Technology Node and Beyond", VLSI Tech. Dig., pp.138-139, 2009.
[5.29] C. Auth, A. Cappellani, J.-S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, N. Rahhal-orabi, P. Ranade, J. Sandford, L. Shifren%, V. Souw, K. Tone, F. Tambwe, A. Thompson, D. Towner, T. Troeger, P. Vandervoorn, C. Wallace, J. Wiedemer, and C. Wiegand, “45nm High-k + Metal Gate Strain-enhanced Transistors”, VLSI Tech. Dig., pp. 128-129, 2008.
[5.30] G. Lucovsky, Y. Wu, H. Niimi, V. Misra, and J. C. Phillips, “Bonding constraint-induced defect formation at Si-dielectric interfaces and internal interfaces in dual-layer gate dielectrics”, J. Vac. Sci. Technol. 817, 1806, 1999.
[5.31] K. P. Cheung, Proc. 6th ISSICT, 315 (2001), (Shanghai).
[5.32] H. Watanabe, “Interface engineering of a ZrO2/SiO2/Si layered structure by in situ reoxidation and its oxygen-pressure-dependent thermal stability”, Appl. Phys. Lett. Vol. 78, 3803, 2001.
[5.33] E. P. Gusev, E. Cartier, D. A. Buchanan, M. Gribelyuk, and M. Copel., AVS Topical Conf. on Atomic Layer Deposition, May 14, 2001
[5.34] M. Ritala and M. Leskela, “ Atomic Layer Deposition,” Handbook of Thin Film Materials, H. S. Nalwa ed., Academic Press, 2001, Vol.1, Chap. 2
[5.35] D. H. Triyoso, R. I. Hegde, B. E. White, and P. J. Tobin , "Physical and Electrical Characteristics of Atomic-Layer-Deposited Hafnium Oxide Formed Using Hafnium Tetrachloride and Tetrakis(ethylmethylaminohafnium)," Jour. of Appl. Physics, vol. 97, 124107, pp. 1-9, 2005.
[5.36] L. Niinistö, M. Nieminen, J. Päiväsaari, J. Niinistö, M. Putkonen, M. Nieminen, "Advanced Electronic and Optoelectronic Materials by Atomic Layer Deposition: An Overview with Special Emphasis on Recent Progress in Processing of High-k Dielectrics and Other Oxide Materials," Physica Status Solidi (a), 201, p. 1443–1452, 2004.
[6.1] Yudong Kim, Gabriel Gebara, Michael Freiler, Joel Barnett, Deborah Riley, Jerry Chen, Kenneth Torres, JaeEun Lim, Brendan Foran, Fred Shaapur, Avinash Agarwal, Patrick Lysaght, George A. Brown, Chadwin Young, Swarnal Borthakur, Hong-Jyh Li, Billy Nguyen, Peter Zeitzoff, Gennadi Bersuker, David Derro, Renate Bergmann, Robert W. Murto, Alex Hou, Howard R. Huff, 'Eric Shero, 'Christophe Pomarede, 'Michael Givens, 'Mike Mazanec, and 'Chris Werkhoven, “Conventional n-channel MOSFET devices using single layer HfO2 and ZrO2 as high-k gate dielectrics with polysilicon gate electrode”, IEDM Tech. Dig. , 2021 (2001).
[6.2] Hyung-Suk Jung, Jong-Ho Lee, Sung Kee Han, Yun-Seok Kim, Ha Jin Lim, Min Joo Kim, Seok Joo Doh, Mi Young Yu, Nae-In Lee ; Hye-Lan Lee, Taek-Soo Jeon, Hag Ju Cho, Sang Bom Kang, Sang Yong Kim, Im Soo Park, Dongchan Kim, Hion Suck Baik, Chung, Young Su, “A highly manufacturable MIPS (metal inserted poly-Si stack) technology with novel threshold voltage control”, Symp. VLSI Tech. Dig., 232 (2005).
[6.3] Hyung-Suk Jung, Tae Joo Park, Kim, Jeong Hwan, Lee, S.Y., Lee, J., Him Chan Oh, Kwang Duck Na, Jung-Min Park, Weon-Hong Kim, Min-Woo Song,; Nae-In Lee, Seong Hwang, Cheol, “Systematic study on bias temperature instability of various high-k gate dielectrics ; HfO2, HfZrxOy and ZrO2”, IRPS., 971 (2009).
[6.4] A. Delabie, M. Caymax, B. Brijs, D. P. Brunco, T. Conard, E. Sleeckx, S. van Elshocht, L.-Å. Ragnarsson, S. De Gendt, and M. Heyns, “Scaling to sub-1 nm equivalent oxide thickness with hafnium oxide deposited by atomic layer deposition”, J. Electrochem. Soc., vol. 153, no. 8, pp. F180–F187, 2006.
[6.5] D. Triyoso, R. Liu, D. Roan, M. Ramon, N. V. Edwards, R. Gregory, D. Werho, J. Kulik, G. Tam, E. Irwin, X.-D. Wang, L. B. La, C. Hobbs, R. Garcia, J. Baker, B. E. White, Jr., and P. Tobin, “Impact of deposition and annealing temperature on material and electrical characteristics of ALD HfO2”, J. Electrochem. Soc., vol. 151, no. 10, pp. F220–F227, 2004.
[6.6] E. P. Gusev, C. Cabral, M. Copel, C. Emic, M. Gribelyuk, “Ultrathin HfO2 film grown on silicon by atomic layer deposition for advanced gate dielectrics applications”, in Microelectronic Engineering, vol. 69 , pp. 145-151, 2003.
[6.7] M. M. Frank, Y. J. Chabal, M. L. Green, A. Delabie, B. Brijs, G. D. Wilk, M.-Y. Ho, E. B. O. da Rosa, I. J. R. Baumvol, and F. C. Stedile, “Enhanced initial growth of atomic-layer-deposited metal oxides on hydrogen-terminated silicon”, Appl. Phys. Lett., vol. 83, no. 4, pp. 740-742, July 2003.
[6.8] M. Cho, R. Degraeve, G. Pourtois, A. Delabie, L. A. Ragnarsson, T. Kauerauf, G. Groeseneken, S. De Gendt, M. M. Heyns, and C. S. Hwang,” Study of the Reliability Impact of Chlorine Precursor Residues in Thin Atomic-Layer-Deposited HfO2 Layers”, IEEE Trans. Electron Devices, vol. 54, no. 4, pp. 752-758, Apr. 2007.
[6.9] J. J. Peterson, C. D. Young, J. Barnett, S. Gopalan, J. Gutt, C.-H. Lee, H.-J. Li, T.-H.Hou, Y. Kim, C. Lim, N. Chaudhary, N. Moumen, B.-H. Lee, G. Bersuker, G. A. Brown, P. M. Zeitzoff, M. I. Gardner, R. W. Murto, and H. R. Huff, “Subnanometer Scaling of HfO2/Metal Electrode Gate Stacks”, Electrochem. Solid-State Lett., vol. 7, iss. 8, G164-G167, 2004
[6.10] J. J. Y. Kuo, W. P. N. Chen, and P. Su, “Impact of uniaxial strain on low-frequency noise in nanoscale”, IEEE Electron Device Letters, vol. 30, no. 6, pp. 672-674, June 2009.
[6.11] C. W. Kuo, S. L. Wu, S. J. Chang, Y. T. Huang, Y. C. Cheng, and O. Cheng, “Impact of stress-memorization technique induced-tensile strain on low frequency noise in n-channel metal-oxide-semiconductor transistors”, Appl. Phys. Lett., Vol. 97, pp. 123501-1~123501-3, Sep. 2010.
[6.12] L. K. J. Vandamme, and F. N. Hooge, “What do we certainly know about 1/f noise in MOSTs,” IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3070-3085, 2008.
[6.13] G. Ghibaudo and T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices”, Microelectron Reliability, vol. 42, pp. 573-582, 2002.
[6.14] M. Toita, L. K. J. Vandamme, S. Sugawa, A. Teramoto, and T. Ohmi., “Geometry and bias dependence of lowfrequency random telegraph signal and 1/f noise levels in MOSFETs,” Fluctuation and Noise Letters, Vol. 5, No. 4, pp.L539-L548, 2005.
[6.15] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Yang, “Random telegraph noise of deep-submicrometer MOSFETs,” IEEE Electron Device Lett., Vol. 11, No. 2, pp. 90-92, Feb. 1990.
[6.16] Bo Chin Wang, San Lein Wu, Chien Wei Huang, Yu Ying Lu, Shoou Jinn Chang, Yu Min Lin, Kun Hsien Lee, and Osbert Cheng “Correlation Between Random Telegraph Noise and 1/f Noise Parameters in 28-nm pMOSFETs With Tip-Shaped SiGe Source/Drain,” IEEE Electron Device Lett., Vol. 33, No. 7, pp. 928-930, 2012.
[7.1] R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Murthy, M. Doczy, R. Arghavani, and S. Datta., “Advanced Depleted-Substrate Transistors: Single-Gate, Double-Gate, and Tri-Gate,” International Conference on Solid-State Devices and Materials (SSDM), Nagoya, Japan, pp. 68-69, 2002.
[7.2] J.-J. Lee, S. T. Hsu, D. J. Tweet, and J.-S. Maa, “Strained silicon finFET device,” U.S. Patent, no. 7045401, May 2006.
[7.3] M. Radosavljevic, G. Dewey, J. M. Fastenau, J. Kavalieros, R. Kotlyar, B. Chu-Kung, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, L. Pan, R. Pillarisetty, W. Rachmady, U. Shah, and R. Chau, “Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications,” Tech. Dig. - Int. Electron Devices Meet., pp. 126-129, 2010.
[7.4] C.-Y. Chang, T.-L. Lee, C. Wann, L.-S. Lai, H.-M. Chen, C.-C. Yeh, C.-S. Chang, C.-C. Ho, J.-C. Sheu, T.-M. Kwok, F. Yuan, S.-M. Yu, C.-F. Hu, J.-J. Shen, Y.-H. Liu, C.-P. Chen, S.-C. Chen, L.-S. Chen, L. Chen, Y.-H. Chiu, C.-Y. Fu, M.-J. Huang, Y.-L. Huang, S.-T. Hung, J.-J. Liaw, H.-C. Lin, H.-H. Lin, L.-T. S. Lin, S.-S. Lin, Y.-J. Mii, E. Ou-Yang, M.-F. Shieh, C.-C. Su, S.-P. Tai, H.-J. Tao, M.-H. Tsai, K.-T. Tseng, K.-W. Wang, S.-B. Wang, J. J. Xu, F.-K. Yang, S.-T. Yang, C.-N. Yeh, “A 25-nm Gate-Length FinFET Transistor Module for 32nm Node,” Tech. Dig. - Int. Electron Devices Meet., pp. 293-296, 2009.
[7.5] R. T.-P. Lee, K.-M. Tan, A. E.-J. Lim, T.-Y. Liow, G. S. Samudra, D.-Z. Chi, and Y.-C. Yeo, “P-Channel Tri-Gate FinFETs Featuring Ni1−yPtySiGe Source/Drain Contacts for Enhanced Drive Current Performance,” IEEE Electron Device Lett., vol. 29, no. 5, pp. 438-441, May 2008.