在現今的電視系統，交錯式影像廣泛地被用來減少廣播時所需的頻寬，因此一個簡單、高效能且低成本的解交錯VLSI電路架構，對目前許多的影像顯示應用是非常必要的。在本篇論文中，我們提出一個新穎的數位影像解交錯邊緣保留電路，使用MDD(motion-degree detector)辨識出連續圖像間移動的程度，包含：靜止(stationary)，微動(slight motion)和移動(motion)三種情況。根據MDD辨識出的移動型態，我們使用一個時間插補(temporal interpolation)方法和兩個空間時間插補(spatial-temporal interpolation)技巧來插補遺失的像素。和其他現存的解交錯方法比較，我們的方法可以更有效的保留邊緣的特徵，而且能以低計算量產生高視覺品質的畫面。
所提出的 VLSI 架構使用 Verilog 硬體描述語言實作，並用 SYNOPSYS 的 Design Vision 和 TSMC’s 0.18 μm 的標準元件庫合成。合成的結果顯示，電路的邏輯閘數目為16.3K。它能以 5 ns 的時脈週期運轉並達到每秒處理 200 百萬像素，此速度能即時處理每秒 30 個 WQSXGA (3200×2048) 格式的影像。

In current television systems, the interlaced video is widely used to reduce the broadcasting bandwidth, so an efficient de-interlacing technique, which is simple and suitable for low-cost VLSI implementation, is necessary for various video display applications. In this thesis, we present a novel edge-preserving VLSI architecture for digital video de-interlacing. The proposed design uses a motion-degree detector to recognize three types of motion between the consecutive images: stationary, slight motion and normal motion. Based on those motion types, we use one temporal interpolation and two spatial-temporal interpolation techniques to interpolate the missing pixels, respectively. Compared with other existing de-interlacing techniques, our design can preserve edge characteristics efficiently and perform better in terms of both quantitative evaluation and visual quality.
The VLSI architecture of the proposed design was implemented by using Verilog HDL. We used SYNOPSYS Design Vision to synthesize the design with TSMC’s 0.18μm cell library. Synthesis results show that the de-interlacing processor contains 16.3K gate counts. It works with a clock period of 5 ns and can achieve a processing rate of 200 mega pixels per second which is quick enough to process a video resolution of WQSXGA (3200×2048) at 30 fps in real time.

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