在現今的科技當中，晶圓製造為其中不可缺的一環，隨著半導體製程的不斷進步，尺寸的微縮成為其中的主流，隨之而來的各種負面效應促使我們尋找改善的方法，而鰭式場效應電晶體也因為克服了短通道效應成為目前先進技術的首選，但是技術節點的持續微縮使得鰭式結構的通道也逐漸再度遭遇短通道效應的困擾，因此在不改變鰭式通道的前提下，改善電晶體電性成為我們的目標。
在本篇論文中，我們利用TCAD建構出鰭式場效應電晶體的模型，參考國際設備和系統路線圖(IRDS)所提供的2020年版3奈米節點尺寸作為基準，並藉由改變電晶體的材料及細微結構來改善通道中的壓力變化，再進一步的觀察其遷移率和Gm的變化，進而達到改善元件的目的。
本實驗主要測量方法為建構不同的模型，如:電晶體通道中的矽鍺比例、鰭式通道的頂部及底部的寬度變化、通道的高度、Fin Pitch和Gate Pitch。再透過TCAD去分析材料與結構改變的遷移率變化，並找出符合技術節點的最佳化模型。

In today's technology, wafer fabrication is one of the indispensable parts. With the continuous advancement of the semiconductor process, size shrinkage has become one of the mainstreams, and the consequent negative effects have prompted us to look for ways to improve it. Therefore, it is our goal to improve the transistor electrical properties without changing the finned channels.
In this thesis, we use TCAD to construct a model of the Fin Field-Effect Transistor and use the 2020 version of the 3 nm technology node provided by the International Roadmap for Devices and Systems (IRDS) as a benchmark and improve the pressure variation in the channel by changing the material and fine structure of the transistor, and then observe the variation of the mobility and Gm to improve the component.
The main measurement method of this experiment is to construct different models, such as the ratio of silicon germanium in the transistor channel, the width changes of the top and bottom of the channel, the height of the channel, Fin Pitch, and Gate Pitch. Then analyze the mobility changes by changing the material and structure through TCAD and find the optimal model that meets the technical nodes.

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