本論文主要包括兩部份: (1) 利用晶格應變技術提昇奈米元件的效能; (2) 極大型積體電路(ULSI)中銅製程技術的最佳化以改善銅導線可靠度。
首先，在本論文中針對不同矽晶格切變應力技術包括全面切變應力技術與局部切變應力技術，甚至基板晶格方向包含面晶格方向與元件通道晶格方向，對元件所產生的優劣特性，有深入的探討。
在本論文中一種新穎製程切變應力技術結合伸展接觸點蝕刻停止膜(tensile CESL)與 <100> 元件通道晶格方向，所產生的應力已成功地同時提升了元件長度與寬度分別為80奈米與0.6微米N型(NMOS)與P型(PMOS)金氧半元件的驅動電流效能分別達 11% 與 35% 之譜。在1.2伏特操作電壓下, 互補式金氧半元件的驅動電流高達 917與436微安培/微米。同樣地，N型(NMOS)與P型(PMOS)金氧半元件的窄通道與反窄通道效應都被有效地壓制。相當優良的閘延遲(gate delay) 與靜態電流(IDDQ) 也都有效地被提昇，閘延遲與靜態電流分別從反向環震盪器(inverter ring oscillator)與微處理器得到高達16%與33%的改善，這是相當正向的成果。
第二部份，將探討銅導線在極大型積體電路中的可靠度，包含銅導線的介電層(IMD)，銅阻絕層(Barrier layer)，銅介電覆蓋層(dielectric capping layer)的效應以及影響銅導線可靠度的理論原理，這些將陳述於本論文中。除此之外，銅雙鑲嵌金屬銅導線表面的清潔對於銅導線電子遷移(Electromigration)與應力誘發空洞(Stress-induced voiding)的影響。在銅擴散阻擋層金屬沉積前，傳統上常利用氬離子撞擊是用來清潔銅表面。較高的偏壓功耗(bias poser)和更短的清潔時間表現出顯著的低連接電阻(via resistance)和銅可靠性效果。此外，導線連接直徑(via diameter) 影響銅電子遷移(stressmigration, SM)也在本論文中被探索。最佳化的銅表面清洗製程將被用來改善電子遷移(Electromigration)與應力誘發空洞(Stress-induced voiding)。氬離子偏壓功耗(bias power)應保持盡可能高但又不能太高，以避免傷害下層的金屬導線，而清潔時間應盡可能短，但長到足以清潔Via底部。隨著極大型積體電路中銅導線製程技術繼續縮小，為了提高產品良率和銅導線可靠性，銅導線表面的清潔製程也將變得越來越重要。

This dissertation includes two parts for nanometer scale CMOSFET device and ULSI technology studying: (1) nano-scale MOSFET enhancement by strained silicon techniques and (2) the process optimization for Cu interconnect reliability.
Firstly, varied device enhancement technology including strained silicon techniques, like global strain and local strain, and substrate orientation, for example of substrate surface orientation and channel orientation, are detailed studied for its pros and cons on device performance.
A novel hybrid process-induced strain techniques by using tensile contact-etch-stop layer (CESL) along <100>-channel direction on (100) surface orientation wafer has demonstrated 11% and 35% driving current enhancement for both bulk NMOS and PMOS simultaneously at gate length/width 80nm/0.6mm. Superior current driving as high as 917 mA/mm and 436 mA/mm for CMOS respectively is achieved at 1.7 nm gate oxide, 80 nm gate length and operation voltage 1.2V. Both narrow width effect (NWE) and reverse narrow width effect (RNWE) are significantly suppressed for PMOSFET and NMOSFET. Excellent gate delay and IDDQ are also improved up to 16% and 33% respectively from inverter ring oscillator (RO) and one microprocessor.
Secondly, the reliability of Cu interconnection in ULSI technology is studied in detail including IMD, Cu barrier layer, Cu dielectric capping layer and electromigration mechanism. In the following, the effects of surface clean process on stressvoiding (SV) and electromigration (EM) of Cu dual damascene metallization are studied. Prior to the deposition of copper diffusion barrier metal, conventional argon bombardment is used to clean Cu surface. Higher pre-clean bias-power and shorter pre-clean time demonstrate remarkable low via resistance and excellent Cu reliability performance. Also, the via diameter effect to Cu stressmigration (SM) is explored. A superior Cu pre-cleaning process condition is developed to improve Cu stress-induced voiding (SIV) and electromigration (EM). The pre-clean bias power of argon plasma should be kept as high as possible but not too high to avoid damaging underlying metal, while the re-sputtering clean time should keep as short as possible but sufficiently long in order to clean via bottoms. To improve ULSI yield and reliability of Cu damascene metallization, the cleaning process of Cu surface becomes more and more critical as CMOS technology continues shrinking

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