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研究生: 任耀傑
Ren, Yao-Jie
論文名稱: 60-GHz CMOS低LO功率、低功耗雙平衡式混頻器與94-GHz整合GIPD晶片天線之CMOS可升降頻單端次諧波電阻式混頻器之毫米波射頻前端的研製
Research on 60-GHz CMOS Low-LO-Power, Low-Power Mixer and 94-GHz RF Frontend with Integrated GIPD Antenna and CMOS Up/Down Single-Ended Subharmonic Resistive Mixer
指導教授: 莊惠如
Chuang, Huey-Ru
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 中文
論文頁數: 118
中文關鍵詞: 60-GHz94-GHzCMOSGIPD天線低功耗混頻器優先弱反轉區偏壓技術可升降頻次諧波混頻器
外文關鍵詞: 60-GHz, 94-GHz, CMOS, GIPD antenna, low-power, mixer-first, weak-inversion biasing technique, up/down sub-harmonic mixer
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  • 本論文設計研製60-GHz低功耗混頻器與94-GHz混頻器優先射頻收發機前端,混頻器皆採用TSMC CMOS 90-nm製程,天線則採用AFSC GIPD製程,透過覆晶技術(flip-chip)由金凸塊(gold bump)與CMOS混頻器異質整合。60-GHz CMOS低LO功率、低功耗降頻混頻器,採用弱反轉區偏壓技術達到低功率消耗及低LO功率,架構移除傳統輸出負載級,利用混頻器核心電晶體直接與轉阻放大器的回授電阻路徑連接,可避免訊號洩漏,造成額外的增益衰減,並能直接提供混頻器核心電晶體所需操作電流。94-GHz整合GIPD天線之CMOS可升降頻混頻器毫米波射頻前端,使用混頻器優先(mixer-first)架構將天線與混頻器直接整合,省去接收路徑低雜訊放大器(LNA)與發射路徑功率放大器(PA)的使用(如應用於極短距離之無線通訊或晶片與晶片間之互聯通訊),可降低系統功率消耗與設計複雜度。混頻器選擇單端被動式架構達到零功率消耗與可升降頻的功能,並採用次諧波混頻原理以減輕未來與壓控振盪器(VCO)整合的設計負擔,天線採用具寬頻特性的對數週期偶極子陣列。電路設計均使用Agilent ADS與全波電磁模擬軟體進行模擬,量測則採以on-wafer方式進行量測,並根據不同的特性參數,調整量測方法與設置。

    This thesis presents the research on 60- and 94-GHz CMOS millimeter-wave (MMW) low-power down-conversion mixer and mixer-first RF transceiver frontend. The designed mixers and antenna are implemented by standard TSMC 90-nm GUTM CMOS process and AFSC general integrated passive device (GIPD) process, respectivity. In the 60-GHz low-LO-power and low-power double-balanced down conversion mixer design, without the traditional load stage, the mixer core is merged directly with self-biased trans-impedance amplifier (TIA) to enhance the conversion gain (CG). By using weak-inversion bias technique in a source-driven topology, the mixer core only needs quiescent current of uA which can be provided from TIA via the feedback resistor. In the 94-GHz integration design of a GIPD log-periodic dipole array (LPDA) antenna (with a balun band-pass filter) and a CMOS up/down single-ended sub-harmonic resistive mixer. The flip-chip technology is used to integrate the GIPD antenna with the CMOS mixer. The LPDA antenna can achieve a wide bandwidth and the balun band-pass filter (BPF) combines the function of the balun and the BPF is to transform the differential signal from the antenna to the single-ended input of the mixer. The sub-harmonic mixer allows the local oscillator (LO) at a half of RF frequency with better phase noise and higher output power than a fundamental mixer (especially at MMW frequency). All the measurements are conducted by fully on-wafer probing. According to different characteristics of the parameters, the measurement methods and setting are adjusted. Simulation and measurement results are compared and discussed.

    第一章 緒論 1 1.1 研究動機與背景 1 1.2 論文架構 3 第二章 60-GHz CMOS低LO功率、低功耗雙平衡式降頻混頻器 5 2.1 混頻器簡介 5 2.1.1 混頻器重要參數設計 7 2.1.2 混頻器種類 14 2.2 60-GHz CMOS 低LO功率、低功耗雙平衡式降頻混頻器 20 2.2.1 弱反轉區偏壓技術 21 2.2.2 LO閘極驅動與源極驅動 27 2.2.3 轉阻放大器 29 2.2.4 馬遜平衡器 30 2.2.5 電路設計說明與考量 33 2.2.6 模擬與量測結果 40 2.3 結果與討論 44 第三章 94-GHz整合GIPD對數週期天線之CMOS可升降頻單端次諧波電阻式混頻器毫米波射頻前端 47 3.1 94-GHz整合晶片架構簡介 47 3.1.1 GIPD對數週期偶極子陣列天線 48 3.1.2 CMOS可升降頻單端次諧波電阻式混頻器 50 3.2 94-GHz整合天線與可升降頻次諧波混頻器之射頻前端晶片設計 52 3.2.1 子電路設計說明與考量 52 3.2.2 子電路模擬結果 55 3.2.3 整合電路模擬與量測結果 63 3.3 結果與討論 69 第四章 結論 73 參考文獻 75 附錄A- 60-GHz混頻器on-wafer雜訊指數量測 81 A.1 Y因子量測法(Y-factor method) 81 A.2 單旁波帶與雙旁波帶雜訊指數 82 A.3 60-GHz混頻器on-wafer雜訊指數量測步驟 85 附錄B- 60-GHz整合GIPD八木天線之CMOS低LO功率、低功耗雙平衡 式降頻混頻器毫米波射頻前端 93 附錄C- Signal-Generator N-times power method雜訊指數量測 111 C.1 雙埠待測物量測 111 C.2 整合晶片之混頻器量測 112

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