於元件應用的發展，將鐵電材料添加至傳統的電晶體結構可以產生不同的工作模式，基於轉移特性可分為兩種：非揮發性模式和陡峭的開關模式。非揮發性模式為鐵電極化特性於記憶體的應用；陡峭的開關模式為串聯一鐵電電容，使次臨界擺幅得以克服波爾茲曼暴增(Boltzmann tyranny)的限制。透過鐵電極化的調變特性，能使鐵電電晶體廣為應用。
目前為主流的高介電係數閘極材料二氧化鉿(HfO2)，基於材料特性的改善，透過添加二氧化鋯(ZrO2)能具有更高的k值，另外摻入鋯元素穩定薄膜正交晶相 (orthorhombic)的之方式，亦能製備具有鐵電性質的氧化層。然而離子鍵組成的高介電係數材料，薄膜缺陷相較於傳統由共價鍵組成的二氧化矽(SiO2)多。在微縮製程的限制下，電晶體閘極堆疊中過薄之界面層，及鐵電極化切換所需的高電場（1-3 MV/cm），將導致更高的電荷俘獲可能性。載子會藉由穿隧的方式注入到HZO/SiO2或SiO2/Si之界面，這些被捕獲的電荷會降低鐵電體的偏振特性，因此尋求如何控制和減少這些缺陷的數量方式，將對鐵電極化的切換帶來顯著的助益！
鐵電電晶體的基本功能可以透過雙向閘極電壓掃描的方式，以汲極電流之遲滯效應做驗證。本研究透過觀察元件於紫外光（UV）照射的電特性響應，針對不同尺寸元件的遲滯方向、遲滯大小做分析與歸納。在研究中，特意將五種不同尺寸的元件換算成各自的比表面積，如此能更客觀地比較不同尺寸元件於光響應的差異。元件經照光會使電晶體的轉移特性進一步改變，從缺陷主導轉變為鐵電主導，其中可能的原因有兩個，一為氧化層的捕獲載子被光激發而降低鐵電性受缺陷的影響，二為光吸收所產生的非平衡載子累積在界面，形成補償電荷，減小鐵電的去極化場。倘若元件本身具有較少的氧化層缺陷，經照光則會得到逆時針遲滯放大，即較明顯的鐵電行為。另外，本研究藉由臨界電壓偏移之現象，以及德拜長度公式推論的結果，輔助闡明所提出的相關論點。然而元件的特性優劣，主要仍取決於氧化層或界面的品質。

For the component applications, adding ferroelectric thin films to the inherent transistor structure can render two different operating modes based on the manipulations of the transistor’s transfer characteristics; namely, the non-volatile and steep switching modes. The non-volatile mode is closely related to the memory operation based on the skillful management of the ferroelectric polarization, while the steep switching mode can be realized by serially cascading some ferroelectric capacitors in a unique sequence to bypass the well-known limitation of Boltzmann tyranny which is considered an unavoidable impediment to the improvement of the subthreshold swing. Through the effective modulation of the ferroelectric polarization, the ferroelectric field-effect transistors can be reliably achieved.
With a suitable mixture of binary metal oxide, the dielectric constant k of the commonly used HfO2 gate oxide can be enhanced by adding a certain percentage of ZrO2 to yield HfxZr1-xO2 (HZO). Furthermore, incorporating the
zirconium element is also proven to be beneficial for stabilizing the orthorhombic phase of the oxide which would reflect the ferroelectric characteristic. Unfortunately, the high-k material composed of ionic bonds has more defects than the traditional silicon dioxide (SiO2). As the device processing continues to miniaturize, the high electric field (1-3 MV/cm) across the thin interfacial layer within the gate stack is typically ferroelectric. required for maintaining ferroelectric polarization would inevitably lead to a higher probability of charge trapping. As carriers are injected into the interface by tunneling, these trapped charges will further destabilize the ferroelectric polarization by enhancing the depolarization field. Controlling and reducing the number of these defects are keys to facilitate the switching of ferroelectric polarization.
The basic functionality of the ferroelectric nanowire transistor can be verified by monitoring the drain current hysteresis during the bidirectional gate voltage scan. Therefore, this study mainly analyzes and summarizes the electrical response of the device to ultraviolet (UV) irradiation; the main emphases will be placed on the rotational direction of the hysteresis window and the width of the hysteresis window when components of different dimensions are compared with one another. To administer the comparisons impartially, the pertinent surface-to-volume ratios of these nanowire transistors are used as the gauging parameters. As the device measurements
would demonstrate, the shrinking of the hysteresis window rotating in a clockwise direction in response to the UV irradiation would indicate that the ferroelectric effect is enhanced. There are two possible reasons. One is that
the trapped carriers of the oxide layer are excited by light to reduce the ferroelectric effect from being affected by defects. The second is that the non- equilibrium carriers due to the UV excitation accumulate at the interface, thereby reducing the depolarization field. On the other hand, if the device itself has fewer defects situated in the oxide layer, the gap of the hysteresis window rotating counterclockwise is expected to enlarge when the device is UV-illuminated, unequivocally showing a sign of the ferroelectric accentuation. Needless to say, the quality of the device itself is still contingent upon the gate oxide robustness and the quality of its adjacent interfaces. And last but not least, the threshold voltage shift and the result of the Debye length formula inferring are also used as an indicator to illuminate the impact of changing polarization effect on the nanoscale devices.

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