可變長度編碼是一種常用的無失真壓縮方法。在本論文裡，提出了一個應用在H.264的低成本可變長度解碼演算法與其VLSI架構設計。一般的可變長度解碼演算法通常需要使用一個相當龐大的字碼表來完成解碼動作，當硬體實現時，為了儲存這樣龐大的表，必須使用到大量的儲存容量，所以需要相當高的成本。為了降低硬體成本，本論文提出一個新的解碼演算法，利用一個較小的解碼表來取代傳統的字碼表，所以只需要少量的記憶體空間與特殊硬體運算模組就可以得到正確的結果，故可大量地降低硬體實現的成本。與先前文獻提出的其他方法比較，本論文所提出的方法大約可以減少35%的儲存容量。所提出的VLSI架構是使用Verilog來設計並以Artisan TSMC 0.18 標準元件庫來合成實現整個電路。依據合成結果，可變長度解碼器所需的gate count數為4000，並可達到125 MHz的工作時脈。

Variable-length coding (VLC) is a very popular lossless compression method. In our thesis, we propose a low-cost VLD (variable-length decoding) method and its VLSI architecture for H.264. Traditionally, the VLD method usually needs to use a quite large decoding table to complete the decoding process. When the VLSI implementation is considered, we need an extensive memory space to store such a large table. Obviously, the cost is high and unacceptable. Instead of storing a full and large decoding table, we propose a novel decoding algorithm which only stores the most representative table and uses some extra mapping and calculating modules to reduce the hardware cost. We can perform decoding correctly by using less memory space and some simple calculating circuits. Thus, the hardware cost of our CAVLD method can be reduced largely. Compared with the previous methods, our CAVLD method can reduce about 35% memory size, and thus need lower hardware cost. The VLSI architecture is designed with Verilog and implemented by using Artisan TSMC 0.18 cell library. According to the synthesis results, the CAVLC decoder contains 4000 gate counts, and can work with a clock rate of 125 MHz.

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