本研究以比較物理氣相沉積濺鍍(PVD sputtering)、電漿輔助原子層沉積(PEALD)及使用N2/H2電漿前處理對碳化矽金氧半電容(SiC MOS Capacitor)閘極介電層品質及介面品質的影響。
首先探討使用PVD濺鍍製備不同厚度的SiO2閘極介電層。在50奈米樣品中，未退火元件在特定電場下，所測得之漏電流密度高達1.90×10-6 A·cm-2，即便經過1小時氮氣退火改善至1.43×10-6 A·cm-2，漏電流密度也僅減少了24.7%。此外，由於高密度SiO2缺陷存在於物理氣相沉積(PVD)製程中，進而導致嚴重漏電，使其C-V曲線產生顯著雜訊與突起變形，樣品整體表現最差
隨後探討以電漿輔助原子層沉積技術所成長之閘極介電層特性，其薄膜緻密性顯著優於物理氣相沉積。在未退火狀態下，50奈米樣品的漏電流密度即大幅壓低至1.04×10-8 A·cm-2，介面態密度（Dit）為2.88 × 1011 cm-2·eV-1。經高溫氮氣退火後，漏電流密度得以再降低至9.41 × 10-9 A·cm-2（較未退火狀態減少9.5%），且介面態密度（Dit）為2.33×1011 cm-2·eV-1，顯著降低19.10%，在所有50奈米樣品中表現最好。
最後於電漿輔助原子層沉積SiO2閘極絕緣層前，引入不同功率（100W至250W）之N2/H2電漿對4H-SiC基板進行表面前處理的電學影響。實驗結果顯示，在未退火狀態下，各功率條件之元件均能將漏電流密度穩定維持在10-8 A·cm-2，具備良好的初始絕緣與抗擊穿能力；然而，電容-電壓（C-V）量測卻呈現嚴重的費米能階釘紮（Fermi-Level Pinning）效應，使電容訊號失去調變能力，主因於長時間電漿轟擊對SiC表面造成物理損傷與介面缺陷。此外，經高溫氮氣後退火1小時後，元件漏電流密度不降反升至約10-2 A·cm-2，顯示絕緣層產生劣化，且過大的漏電流嚴重干擾C-V訊號，致使曲線顯著失真並無法精確萃取介面態密度（Dit）等關鍵參數。綜合所述，N2/H2電漿前處理所引發的表面物理損傷及隨後高溫退火帶來的膜質劣化，使其無法達到有效鈍化介面與提升元件品質的預期目標。

This study compares the effects of physical vapor deposition (PVD) sputtering, plasma-enhanced atomic layer deposition (PEALD), and the introduction of N2/H2 plasma pre-treatment on the properties of both the gate oxide and the interface of silicon carbide metal-oxide-semiconductor capacitors (SiC MOS Capacitor).
First, the preparation of SiO2 gate insulating layers with varying thicknesses using PVD sputtering was investigated. Among the 50 nm samples, the unannealed device exhibited a leakage current density as high as 1.90×10-6 A·cm-2 under a fixed electric field. Even after a 1-hour nitrogen annealing treatment, which improved it to 1.43×10-6 A·cm-2, the leakage current density was only reduced by 24.7%. Furthermore, due to high density SiO2 defects, the PVD method caused severe leakage, causing significant noise interference and abnormal hump distortion in its C–V curves, resulting in the worst overall performance.
Subsequently, the characteristics of the gate insulating layer prepared by PEALD were investigated, showing a film density significantly superior to that of PVD. In the unannealed state, the leakage current density of the 50 nm sample was drastically suppressed to 1.04×10-8 A·cm-2, with an interface state density (Dit) was measured to be 2.88 × 1011 cm-2·eV-1. After high-temperature N2 annealing, the leakage current density further decreased to 9.41 × 10-9 A·cm-2 (decreased 9.5% compared to the unannealed sample). Meanwhile, the interface state density Dit dropped to2.33×1011 cm-2·eV-1, representing a significant reduction of 19.10%, demonstrating the best performance among all 50 nm samples.
Finally, the electrical impacts of introducing an N2/H2 plasma pre-treatment under various plasma powers (100W to 250W) on the 4H-SiC substrate prior to the plasma-enhanced atomic layer deposition of the SiO2 gate dielectric layer were investigated. Experimental results showed that in the unannealed state, devices under all plasma power conditions stably maintained a low leakage current density on the order of 10-8A·cm-2, exhibiting good initial insulation and breakdown resistance. However, capacitance–voltage (C-V) measurements presented severe Fermi-level pinning effects, causing the capacitance signal to lose its modulation capability. This was primarily attributed to physical damage and interface defects on the SiC surface caused by prolonged plasma bombardment. Furthermore, after high-temperature nitrogen annealing for 1 hour, the leakage current density of the devices increased rather than decreased to approximately 10-2A·cm-2, indicating degradation of the insulating layer. The excessively high leakage current severely interfered with the C-V signals, causing pronounced curve distortion and rendering the accurate extraction of key parameters, such as the interface state density (Dit), impossible. In summary, the surface physical damage induced by the N2/H2 plasma pre-treatment, along with the film quality degradation caused by subsequent high-temperature annealing, failed to achieve the expected goal of effectively passivating the interface and improving device quality.

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