在本論文中，我們探討了不同通道寬度的p型通道金氧半電晶體的熱載子可靠度與元件特性。我們在本次實驗中使用了p型MOSFETs，分別為I/O元件:尺寸為L =0.24μm, W = 10μm、5μm、1μm，閘極氧化層厚度為44Å；與core元件:尺寸為L= 0.06μm, W = 5μm、1μm and 0.07um，閘極氧化層厚度為20Å。I/O元件其熱載子實驗加壓在Vg@ Ig (max)、Vg@ Isub(max)、Vg=Vd的條件下；而core元件則是加壓在Vg=Vd的條件下。在固定熱載子加壓測試下，利用I-V量測定義物理特性和討論熱載子造成的退化現象和機制。
我們發現實驗結果為窄的通道產生較多的氧化缺陷電荷，造成熱載子損傷比較嚴重。我們推測窄通道具有較高的電場而導致退化增加。而在p-MOS熱載子可靠度的研究也利用了charge pumping分析，來討論和觀察在不同加壓和寬度的條件下其元件退化機制，包括缺陷種類(介面缺陷(Nit)和/或是 氧化層缺陷(Not))。

　 In this thesis, hot carrier reliability and device characteristics of p-channel MOS transistors with different channel width are investigated.
　　　The p-MOSFETs used in this experiments performed have I/O devices: L =0.24μm, W = 10μm、5μm、1μm with gate oxide thickness of 44Å and core devices: L = 0.06μm, W = 5μm、1μm and 0.07um with gate oxide thickness of 20Å. I/O devices stressing are performed at Vg@ Ig (max)、Vg@ Isub(max)、Vg=Vd condition and core devices stressing are performed at Vg=Vd condition. After constant voltage hot carrier stress were performed, I-V measurements were used to characterize the physical properties and discuss the hot carrier degradation phenomenon and mechanism.

　　We discovered the experimental results, hot carrier induced degradation is more significant in narrow channel by the generations of interface states and oxide trapped charges. We presumable that the narrow channel has high lateral electric field which causes degradation increase. And the hot carrier reliability of PMOS was investigated by charge pumping analysis, device degradation mechanisms are discussed and observed, including trap properties (interface traps (Nit) and/or oxide traps (Not)) under various width and stress conditions.

[1] Shuang-Yuan Chen, Chia-Hao Tu, Jung-Chun Lin, Mu-Chun Wang, Po-Wei Kao, Memg-Hong Lin, Ssu-Han Wu, Ze-Wei Jhou, Sam Chou, Joe Ko, and Heng-Sheng Haung “Investigation of DC Hot-Carrier Degradation at Elevated Temperatures for p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors of 0.13um Technology” Japanese Journal of Applied Physics vol. 47, no. 3, (2008), pp. 1527-1531
[2] Jone F. Chen, Kuen-Shiuan Tian, Shiang-Yu Chen, Kuo-Ming Wu, J. R. Shih, and Kenneth Wu, ”Mechanisms of Hot-Carrier-Induced Threshold-Voltage Shift in High-Voltage p-Type LDMOS Transistors.” IEEE Trans. Elect. Dev. vol.56, no. 12, Dec. (2009),pp. 3203-3206.
[3] C. Y. Chang and S. M. Sze, “ULSI Technology,” (1996).
[4] R. Woltjer, G. M. Paulzen, H. Lifka, and P. Woerlee, “Positive Oxide-Charge Generation During 0.25um PMOSFET Hot-Carrier Degradation.” IEEE Electron Device Letters, vol.15, no.10, Oct. (1994),pp. 427-429.
[5] R. Woltjer, Ger M. Paulzen, Henk G. Pomp, Herbert Lifka, and Pierre H. Woerlee, ”Three Hot-Carrier Degradation Mechanisms in Deep-Submicron PMOSFET’s” IEEE Trans. Elect. Dev. vol.42, no. 1, Jan. (1995),pp. 109-114.
[6] D.P. Ioannou, R. Mishra, D.E. Ioannou, S.T. Liu, H.L. Hughes, “Worst case stress condition for hot carrier induced degradation of p-channel SOI MOSFETs.” Solid-State Electronics 50 (2006) ,pp. 929-934
[7] A. Schwerin, W. Hansch, and W. Weber, “The relationship between Oxide charge and device degradation: A comparative study of n- and p- channel MOSFET's”, IEEE Trans. Electron Devices, vol. 34, no. 12, Dec. (1987) , pp. 2493-2500.
[8] E. Takeda, C. Yang, A. Miura-Hamada, “Hot-carrier effects in MOS Devices,” Academic Press (1995).
[9] A. Melik-Martirosian and T. P. Ma, “Improved charge-pumping method for Lateral Profiling of interface traps and oxide charge in MOSFET Devices,” IEDM (1999), pp. 93-96.
[10] D. K. Schroder, “Semiconductor Material and Device haracterization,” third edition (2006).
[11] C. C. Cheng, K. C. Tu, and T. Wang, “Investigation of Hot Carrier Degradation Modes in LDMOS by Using A Novel Three-region Charge Pumping Technique,” IEEE IRPS (2006), pp. 334-337.
[12] K.Ohe et al., “Narrow-width effects of shallow trench-isolated CMOS with n+-polysilicon gate,” IEEE Trans. On Electron Devices, Vol. 36, No. 6, June (1998), pp . 1110-1116.
[13] W.S. Lau, K.S. See, C.W. Eng, W.K. Aw, K.H. Jo, K.C. Tee, James Y.M. Lee, Elgin K.B. Quek, H.S. Kim, Simon T.H. Chen, L. Chan, “Anomalous narrow width effect in p-channel metal-oxide-semiconductor surface channel transistors using shallow trench isolation technology,” Microelectronics Reliability 48 (2008), pp. 919-922.
[14] Christian Pacha, Martin Bach, Klaus von Arnim, Ralf Brederlow, Doris Schmitt-Landsiedel, Peter Seegebrecht, Jorg Berthold, and Roland Thewes, “Impact of STI-Induced Stress, Inverse Narrow Width Effect, and Statistical VTH Variations on Leakage Currents in 120 nm CMOS,” IEEE (2004), pp. 379-400.
[15] S. S. Chung, S. J. Chen, W. J. Yang, C. M. Yih and J. J. Yang, “ New Degradation Mechanisms of Width-Dependnt Hot Carrier Effect in Quarter Micron Shallow-Trench-Isolated p-Channel Metal-Oxide-Semiconductor Field-Effect-Transistors,” Jan. J. Appl. Phys. Vol. 40 (2001), pp.69-74.
[16] Kazunari Ishimaru, Jone F. Chen and Chenming Hu, “Channel Width Dependence of Hot-Carrier Induced Degradation in Shallow trench Isolated PMOSFETs,” IEEE transactions on electron devices. Vol. 46, NO. 7, July (1999), pp. 1532-1535.
[17] M.Nishigohri, K.Ishimaru, M.Takahashi, Y.Unno, Y.Okayama, F.Matsuoka, nad M.Kinugawa, “Anomalous Hot-carrier Induced Degradation in Very Narrow Channel nMOSFETs with STI Structure,” IEEE (1996),pp. 881-884.
[18] W. H. T. Phua, D. S. Ang, C. H. Ling and K. J. Chui, “STI-Induced Damage and Hot-Carrier Reliability in the Narrow Width Short Channel NMOSFET Fabricated Using Global Strained-Si Technology,” Proceedings of ESSDERC, Grenoble, France, (2005), pp. 533-536.
[19] Y.-H. Lee, K. Wu, T. Linton, N. Mielke, S. Hu, and B. Wallace, “Channel-Width Dependent Hot-Carrier Degradation of Thin-Gate pMOSFETs,” IEEE (2000),pp. 77-82.
[20] S. S. Chung, S. J. Chen, W. J. Yang, and J. J. Yang, “A new physical and quantitative width dependent hot carrier model for shallow-trench-isolated CMOS devices,” in Proc. IRPS, Orlando, FL, 2001, pp. 419-424.
[21] S. S. Chung, C. H. Yeh, S. J. Feng, C. S. Lai, J. J. Yang, C. C. Chen, Y. Jin, S. C. Chen and M. S. Liang, “Impact of STI on the Reliability of Narrow-Width pMOSFETs With Advanced ALD N/O Gate Stack,” IEEE transactions on device and materials reliability, VOL. 6, NO. 1, MARCH (2006),pp. 95-101.
[22] S. S. Chung, C. H. Yeh, S. J. Feng, C. S. Lai, J. J. Yang, C. C. Chen, Y. Jin, S. C. Chen and M. S. Liang, “The Impact of STI Induced Reliabilities for Scaled p-MOSFET in an Advanced Multiple Oxide CMOS Technology,” IEEE (2004), pp. 279-282.