在本論文中，我們針對不同佈局參數的高壓金氧半場效電晶體元件的特性以及熱載子可靠度進行深入討論並解釋物理機制。重要的佈局參數分別為L、G及S。分別對應到閘極長度、飄移區的長度與淺溝槽隔離(STI)和汲極之間的長度。
在本論文中，首先會先簡單介紹目前高壓元件在市場的應用，並介紹熱載子效應與崩潰機制的基本原理。接著介紹在本論文中所用到的元件結構及基本電性的量測。為了更深入了解元件內部的物理機制，將使用電腦輔助設計(TCAD)來進行模擬分析。
第二部分則會藉由基本電性的量測，觀察不同位置的佈局參數對元件特性的影響。並預期L或G的減少會增強線性區電流和飽和區電流，特別是縮短L會使飽和區電流增加最多。另一方面，縮短G可使線性區電流有最多的增加。
第三部分則是操作電壓對熱載子效應所引起的元件退化的影響，結果顯示在低閘極電壓的情況下有較大的退化。隨著介面缺陷的增加，會使間隙物底部附近的電位分佈會發生變化，從而重新分佈電場，同時減少碰撞電離，並導致了退化飽和的現象。根據實驗結果，表明元件的退化是在間隙物下方由熱載子引起的介面缺陷生成。推測兩種熱載子都應參與元件的退化，主要的區別在於兩個載子的比率。在低閘極電壓下，熱電洞對退化的貢獻更大。當閘極電壓超過5.75V時，熱電子對退化的貢獻將逐漸增加。此外，本研究中評估熱載子所引起的退化時，除了要考慮峰值碰撞游離率的大小以外，還應考慮垂直電場的大小
第四部分則是佈局參數對於元件的熱載子生命週期以及崩潰電壓機制的影響。微縮參數L和G將大大地影響元件的電特性和可靠度。然而，微縮參數S則僅影響崩潰電壓，並且對電流特性和熱載子生命週期的影響較小。

In this thesis, we investigate the mechanism of hot-carrier-induced degradation and characteristics of the N-type high voltage metal-oxide-semiconductor with different layout parameters. The important layout parameters L, G, and S. They correspond to the length of the gate, the length of the drift region, and the length between drain contact and shallow trench isolation (STI), respectively.
In this thesis, we will first briefly introduce the application of high-voltage devices in the market and the basic mechanism of the device. Subsequently, we will introduce the device structure and basic electrical characteristics used in this thesis. To gain a deeper understanding of the physical mechanism inside the device, TCAD will be used for analysis.
The second part is will observe the influence of the layout parameters at different positions on the characteristics of the device through basic electrical measurement. It is expected that the decrease of L or G enhances IDlin and IDsat, especially shortening L increases IDsat the most. On the other hand, shortening G increases IDlin the most.
The third part is the effect of gate voltage on hot-carrier degradation. The results show that there is a greater degradation at low gate voltage. As Nit increases, the potential distribution near the bottom of the spacer changes, redistributing the electric field, resulting in less impact ionization and saturating degradation. According to the results, it shows that the dominant degradation of the device is the hot-carrier induced Nit generation under the spacer. It is speculated that both hot carriers should participate in the degradation of the device. The main difference is the ratio of the two carriers.
At the low gate voltage, the contribution of hot holes to the degradation is greater. When the gate voltage exceeds 5.75V, the contribution of hot electrons to the degradation will gradually increase. Besides, not only the magnitude of the peak impact ionization rate, but also the magnitude of the vertical electric field should be considered when evaluating the hot-carrier induced degradation in this study.
The fourth part is the effect of layout parameters on the hot-carrier lifetime and breakdown voltage mechanism of the device. The scaling parameters L and G will greatly affect the characteristics and reliability of the device. However, the scaling parameter S affects the breakdown voltage, but has little effect on the current and hot carrier lifetime.

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