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研究生: 邱恒伃
Chiu, Heng-Yu
論文名稱: 可抑制交流抵補電壓之電容式單軸加速器設計
Design of a Single-Axis Capacitive Accelerometer with AC Offset Cancellation Circuit
指導教授: 魏嘉玲
Wei, Chia-Ling
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 中文
論文頁數: 89
中文關鍵詞: 交流抵補電壓抑制電容式加速度感測器全差分電容電橋訊號處理電路
外文關鍵詞: AC Offset Cancellation Circuit, Capacitive Accelerometer, Fully Differential Capacitive Bridge, Signal Processing Circuit
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  • 有鑑於現今台灣少子化的現象,未來可能會面臨到醫療人力嚴重不足,因此目前趨勢是結合穿戴式醫療裝置、遠端醫療、雲端系統等科技來減輕人力負荷。為了將加速度感測器應用於穿戴式裝置上,本論文實現一單軸電容式加速度感測系統,選用CMOS-MEMS製程設計電容式加速度感測器,並且定期重置電容橋輸出,減少來自感測器電容充放電所造成的輸出偏壓偏移。此外,透過後端處理電路的交流抵補電壓抑制技術,消除前端電容式加速度感測器不匹配所產生之交流抵補電壓,以免在高放大倍率時輸出訊號飽和。藉由將感測器與積體電路整合於單晶片,降低加速規的體積與成本。
    本晶片使用台積電(TSMC) 0.35 μm CMOS/MEMS 2P4M 3.3V 混合訊號製程加上微機電後製程製作,以40 S/B 封裝,晶片總面積為2.429×2.068mm2,包含感測器及訊號處理電路。由加速度振動量測平台(Shaker)提供加速度應力,此晶片在±8g的感測範圍下有69.11(mVpp/g)的靈敏度,全系統含感測器的總消耗功率為1.89mW。

    Owing to the recent trend of fewer children and more elders in Taiwan, we might face the shortage of the medical personnel in the future. One of the solutions is to combine high technologies, such as wearable devices, telemedicine, and cloud computing, with hospitals, so that it can lessen the burden on caregivers. In order to apply the accelerometer to wearable devices, a single-axis capacitive accelerometer system has been implemented, whose sensor is made by micro-electromechanical system (MEMS) process. The capacitor bridge outputs are reset to dc voltage regularly for reducing the bias voltage drift caused by the undesirable charging and discharging from the capacitive accelerometer. Besides, an ac offset cancellation loop is proposed to suppress the offset voltage originated from the mismatches in the MEMS sensor, so the mismatch-induced offset would not saturate the chip output. The integration of the MEMS sensor and the complementary metal-oxide-semiconductor (CMOS) circuits significantly reduces the instrument size and costs.

    The proposed chip, fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) 0.35μm 2P4M mixed-signal standard CMOS process and MEMS post process, consists of the front-end sensor and the back-end signal processing circuits, and it occupies 2.429×2.068-mm2 area. The measured sensitivity is 69.11(mVpp/g) within the ±8g sensing range, and the power consumption of the chip is 1.89mW with a 3.3V power supply.

    目錄 第1章 簡介 1 1-1 研究動機 1 1-2 論文架構 2 第2章 文獻探討 3 2-1 加速度器感測技術 3 2-2 電容式加速器系統研究近況 6 2-2-1. 電容式加速器前端感測電路類型 7 2-2-2. 製程變異導致電容不匹配之解決方案 12 第3章 系統架構與電路設計 17 3-1 系統介紹 17 3-2 前一版本量測問題 18 3-3 CMOS-MEMS 電容式加速度感測器 20 3-3-1. 微機電製程介紹 20 3-3-2. 電容式加速度感測器設計與模擬 21 3-4 全差分電容電橋(Fully Differential Capacitive Bridge) 23 3-5 電路設計與功能介紹 30 3-5-1. 緩衝器(Input Buffer) 31 3-5-2. 主要放大電路(Main Amplifier) 34 3-5-3. 截波器(Chopper) 36 3-5-4. 超大時間常數切換電容式積分器(VLT-SC Integrator) 37 3-5-5. 可調式放大電路(Programmable Gain Amplifier, PGA) 42 3-5-6. 六階雙端轉單端切換電容式低通濾波器(Differential to Single-Ended Switched-Capacitor 6th Low Pass Filter) 44 3-5-7. 時脈產生電路(Clock Supply Circuit) 48 第4章 模擬結果 52 4-1 電容式加速度感測器模擬 52 4-1-1. 感測器加速度分析 52 4-1-2. 感測器共振頻率分析 53 4-2 全差分電容電橋模擬 54 4-2-1. 無交流抵補電壓雜訊 55 4-2-2. 具交流抵補電壓雜訊 55 4-3 加速器後端子電路模擬 57 4-3-1. 緩衝器放大器 57 4-3-2. 其餘電路使用之放大器 58 4-3-3. 時脈產生電路 59 4-3-4. 六階雙端轉單端切換電容式低通濾波器 61 4-4 全系統模擬 62 4-4-1. 無交流抵補電壓雜訊 65 4-4-2. 具交流抵補電壓雜訊 65 第5章 量測結果 67 5-1 量測環境與儀器 67 5-2 量測結果 69 5-2-1. 微機電電容式加速度感測器 70 5-2-2. 非重疊時脈 74 5-2-3. 全系統量測結果 76 5-2-4. 非理想效應 80 5-2-5. 緩衝器輸出 81 5-2-6. 低通濾波器 83 5-3 規格比較表 84 第6章 結論與未來展望 86 參考文獻 87

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